Change SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE to chromebook_link which is currently the only real board officially supported to run U-Boot loaded by coreboot.
Note the symbolic link file chromebook_link.dts is deleted and link.dts is renamed to chromebook_link.dts.
To avoid multiple definition of video_hw_init, the CONFIG_VIDEO_X86 define needs to be moved to arch/x86/cpu/ivybridge/Kconfig.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
---
Changes in v4: - Rebase to u-boot-x86/next
Changes in v3: - Move CONFIG_VIDEO_X86 to drivers/video/Kconfig
Changes in v2: - New patch to make chromebook_link the default board for coreboot
arch/x86/dts/Makefile | 3 +- arch/x86/dts/chromebook_link.dts | 217 +++++++++++++++++++++++++++++++++++++- arch/x86/dts/link.dts | 216 ------------------------------------- board/coreboot/coreboot/Kconfig | 4 +- configs/chromebook_link_defconfig | 1 + configs/coreboot-x86_defconfig | 1 - drivers/video/Kconfig | 8 ++ include/configs/chromebook_link.h | 1 - 8 files changed, 228 insertions(+), 223 deletions(-) mode change 120000 => 100644 arch/x86/dts/chromebook_link.dts delete mode 100644 arch/x86/dts/link.dts
diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile index 5525094..97ed884 100644 --- a/arch/x86/dts/Makefile +++ b/arch/x86/dts/Makefile @@ -1,5 +1,4 @@ -dtb-y += link.dtb \ - chromebook_link.dtb \ +dtb-y += chromebook_link.dtb \ crownbay.dtb
targets += $(dtb-y) diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts deleted file mode 120000 index 6f8c5cd..0000000 --- a/arch/x86/dts/chromebook_link.dts +++ /dev/null @@ -1 +0,0 @@ -link.dts \ No newline at end of file diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts new file mode 100644 index 0000000..9490b16 --- /dev/null +++ b/arch/x86/dts/chromebook_link.dts @@ -0,0 +1,216 @@ +/dts-v1/; + +/include/ "skeleton.dtsi" +/include/ "serial.dtsi" + +/ { + model = "Google Link"; + compatible = "google,link", "intel,celeron-ivybridge"; + + config { + silent_console = <0>; + }; + + gpioa { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0 0x10>; + bank-name = "A"; + }; + + gpiob { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x30 0x10>; + bank-name = "B"; + }; + + gpioc { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x40 0x10>; + bank-name = "C"; + }; + + chosen { + stdout-path = "/serial"; + }; + + spd { + compatible = "memory-spd"; + #address-cells = <1>; + #size-cells = <0>; + elpida_4Gb_1600_x16 { + reg = <0>; + data = [92 10 0b 03 04 19 02 02 + 03 52 01 08 0a 00 fe 00 + 69 78 69 3c 69 11 18 81 + 20 08 3c 3c 01 40 83 81 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 0f 11 42 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 02 fe 00 + 11 52 00 00 00 07 7f 37 + 45 42 4a 32 30 55 47 36 + 45 42 55 30 2d 47 4e 2d + 46 20 30 20 02 fe 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00]; + }; + samsung_4Gb_1600_1.35v_x16 { + reg = <1>; + data = [92 11 0b 03 04 19 02 02 + 03 11 01 08 0a 00 fe 00 + 69 78 69 3c 69 11 18 81 + f0 0a 3c 3c 01 40 83 01 + 00 80 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 0f 11 02 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 80 ce 01 + 00 00 00 00 00 00 6a 04 + 4d 34 37 31 42 35 36 37 + 34 42 48 30 2d 59 4b 30 + 20 20 00 00 80 ce 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00]; + }; + micron_4Gb_1600_1.35v_x16 { + reg = <2>; + data = [92 11 0b 03 04 19 02 02 + 03 11 01 08 0a 00 fe 00 + 69 78 69 3c 69 11 18 81 + 20 08 3c 3c 01 40 83 05 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 0f 01 02 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 80 2c 00 + 00 00 00 00 00 00 ad 75 + 34 4b 54 46 32 35 36 36 + 34 48 5a 2d 31 47 36 45 + 31 20 45 31 80 2c 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + ff ff ff ff ff ff ff ff + ff ff ff ff ff ff ff ff + ff ff ff ff ff ff ff ff + ff ff ff ff ff ff ff ff + ff ff ff ff ff ff ff ff + ff ff ff ff ff ff ff ff + ff ff ff ff ff ff ff ff + ff ff ff ff ff ff ff ff + ff ff ff ff ff ff ff ff + ff ff ff ff ff ff ff ff]; + }; + }; + + spi { + #address-cells = <1>; + #size-cells = <0>; + compatible = "intel,ich9"; + spi-flash@0 { + reg = <0>; + compatible = "winbond,w25q64", "spi-flash"; + memory-map = <0xff800000 0x00800000>; + }; + }; + + pci { + sata { + compatible = "intel,pantherpoint-ahci"; + intel,sata-mode = "ahci"; + intel,sata-port-map = <1>; + intel,sata-port0-gen3-tx = <0x00880a7f>; + }; + + gma { + compatible = "intel,gma"; + intel,dp_hotplug = <0 0 0x06>; + intel,panel-port-select = <1>; + intel,panel-power-cycle-delay = <6>; + intel,panel-power-up-delay = <2000>; + intel,panel-power-down-delay = <500>; + intel,panel-power-backlight-on-delay = <2000>; + intel,panel-power-backlight-off-delay = <2000>; + intel,cpu-backlight = <0x00000200>; + intel,pch-backlight = <0x04000000>; + }; + + lpc { + compatible = "intel,lpc"; + #address-cells = <1>; + #size-cells = <1>; + gen-dec = <0x800 0xfc 0x900 0xfc>; + intel,gen-dec = <0x800 0xfc 0x900 0xfc>; + intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b + 0x80 0x80 0x80 0x80>; + intel,gpi-routing = <0 0 0 0 0 0 0 2 + 1 0 0 0 0 0 0 0>; + /* Enable EC SMI source */ + intel,alt-gp-smi-enable = <0x0100>; + + cros-ec@200 { + compatible = "google,cros-ec"; + reg = <0x204 1 0x200 1 0x880 0x80>; + + /* Describes the flash memory within the EC */ + #address-cells = <1>; + #size-cells = <1>; + flash@8000000 { + reg = <0x08000000 0x20000>; + erase-value = <0xff>; + }; + }; + }; + }; + + microcode { + update@0 { +#include "microcode/m12306a9_0000001b.dtsi" + }; + }; + +}; diff --git a/arch/x86/dts/link.dts b/arch/x86/dts/link.dts deleted file mode 100644 index 9490b16..0000000 --- a/arch/x86/dts/link.dts +++ /dev/null @@ -1,216 +0,0 @@ -/dts-v1/; - -/include/ "skeleton.dtsi" -/include/ "serial.dtsi" - -/ { - model = "Google Link"; - compatible = "google,link", "intel,celeron-ivybridge"; - - config { - silent_console = <0>; - }; - - gpioa { - compatible = "intel,ich6-gpio"; - u-boot,dm-pre-reloc; - reg = <0 0x10>; - bank-name = "A"; - }; - - gpiob { - compatible = "intel,ich6-gpio"; - u-boot,dm-pre-reloc; - reg = <0x30 0x10>; - bank-name = "B"; - }; - - gpioc { - compatible = "intel,ich6-gpio"; - u-boot,dm-pre-reloc; - reg = <0x40 0x10>; - bank-name = "C"; - }; - - chosen { - stdout-path = "/serial"; - }; - - spd { - compatible = "memory-spd"; - #address-cells = <1>; - #size-cells = <0>; - elpida_4Gb_1600_x16 { - reg = <0>; - data = [92 10 0b 03 04 19 02 02 - 03 52 01 08 0a 00 fe 00 - 69 78 69 3c 69 11 18 81 - 20 08 3c 3c 01 40 83 81 - 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 - 00 00 00 00 0f 11 42 00 - 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 - 00 00 00 00 00 02 fe 00 - 11 52 00 00 00 07 7f 37 - 45 42 4a 32 30 55 47 36 - 45 42 55 30 2d 47 4e 2d - 46 20 30 20 02 fe 00 00 - 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00]; - }; - samsung_4Gb_1600_1.35v_x16 { - reg = <1>; - data = [92 11 0b 03 04 19 02 02 - 03 11 01 08 0a 00 fe 00 - 69 78 69 3c 69 11 18 81 - f0 0a 3c 3c 01 40 83 01 - 00 80 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 - 00 00 00 00 0f 11 02 00 - 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 - 00 00 00 00 00 80 ce 01 - 00 00 00 00 00 00 6a 04 - 4d 34 37 31 42 35 36 37 - 34 42 48 30 2d 59 4b 30 - 20 20 00 00 80 ce 00 00 - 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00]; - }; - micron_4Gb_1600_1.35v_x16 { - reg = <2>; - data = [92 11 0b 03 04 19 02 02 - 03 11 01 08 0a 00 fe 00 - 69 78 69 3c 69 11 18 81 - 20 08 3c 3c 01 40 83 05 - 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 - 00 00 00 00 0f 01 02 00 - 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 - 00 00 00 00 00 80 2c 00 - 00 00 00 00 00 00 ad 75 - 34 4b 54 46 32 35 36 36 - 34 48 5a 2d 31 47 36 45 - 31 20 45 31 80 2c 00 00 - 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 - ff ff ff ff ff ff ff ff - ff ff ff ff ff ff ff ff - ff ff ff ff ff ff ff ff - ff ff ff ff ff ff ff ff - ff ff ff ff ff ff ff ff - ff ff ff ff ff ff ff ff - ff ff ff ff ff ff ff ff - ff ff ff ff ff ff ff ff - ff ff ff ff ff ff ff ff - ff ff ff ff ff ff ff ff]; - }; - }; - - spi { - #address-cells = <1>; - #size-cells = <0>; - compatible = "intel,ich9"; - spi-flash@0 { - reg = <0>; - compatible = "winbond,w25q64", "spi-flash"; - memory-map = <0xff800000 0x00800000>; - }; - }; - - pci { - sata { - compatible = "intel,pantherpoint-ahci"; - intel,sata-mode = "ahci"; - intel,sata-port-map = <1>; - intel,sata-port0-gen3-tx = <0x00880a7f>; - }; - - gma { - compatible = "intel,gma"; - intel,dp_hotplug = <0 0 0x06>; - intel,panel-port-select = <1>; - intel,panel-power-cycle-delay = <6>; - intel,panel-power-up-delay = <2000>; - intel,panel-power-down-delay = <500>; - intel,panel-power-backlight-on-delay = <2000>; - intel,panel-power-backlight-off-delay = <2000>; - intel,cpu-backlight = <0x00000200>; - intel,pch-backlight = <0x04000000>; - }; - - lpc { - compatible = "intel,lpc"; - #address-cells = <1>; - #size-cells = <1>; - gen-dec = <0x800 0xfc 0x900 0xfc>; - intel,gen-dec = <0x800 0xfc 0x900 0xfc>; - intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b - 0x80 0x80 0x80 0x80>; - intel,gpi-routing = <0 0 0 0 0 0 0 2 - 1 0 0 0 0 0 0 0>; - /* Enable EC SMI source */ - intel,alt-gp-smi-enable = <0x0100>; - - cros-ec@200 { - compatible = "google,cros-ec"; - reg = <0x204 1 0x200 1 0x880 0x80>; - - /* Describes the flash memory within the EC */ - #address-cells = <1>; - #size-cells = <1>; - flash@8000000 { - reg = <0x08000000 0x20000>; - erase-value = <0xff>; - }; - }; - }; - }; - - microcode { - update@0 { -#include "microcode/m12306a9_0000001b.dtsi" - }; - }; - -}; diff --git a/board/coreboot/coreboot/Kconfig b/board/coreboot/coreboot/Kconfig index f2cd754..981de1f 100644 --- a/board/coreboot/coreboot/Kconfig +++ b/board/coreboot/coreboot/Kconfig @@ -13,14 +13,14 @@ comment "coreboot-specific options"
config SYS_CONFIG_NAME string "Board configuration file" - default "coreboot" + default "chromebook_link" help This option selects the board configuration file in include/configs/ directory to be used to build U-Boot for coreboot.
config DEFAULT_DEVICE_TREE string "Board Device Tree Source (dts) file" - default "link" + default "chromebook_link" help This option selects the board Device Tree Source (dts) file in arch/x86/dts/ directory to be used to build U-Boot for coreboot. diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig index b83803e..e956835 100644 --- a/configs/chromebook_link_defconfig +++ b/configs/chromebook_link_defconfig @@ -6,5 +6,6 @@ CONFIG_OF_SEPARATE=y CONFIG_DEFAULT_DEVICE_TREE="chromebook_link" CONFIG_HAVE_MRC=y CONFIG_SMM_TSEG_SIZE=0x800000 +CONFIG_VIDEO_X86=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y CONFIG_FRAMEBUFFER_VESA_MODE_11A=y diff --git a/configs/coreboot-x86_defconfig b/configs/coreboot-x86_defconfig index 6249db7..3cc034a 100644 --- a/configs/coreboot-x86_defconfig +++ b/configs/coreboot-x86_defconfig @@ -2,4 +2,3 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x01110000" CONFIG_X86=y CONFIG_TARGET_COREBOOT=y CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="link" diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index e69de29..fdbf3f6 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -0,0 +1,8 @@ +config VIDEO_X86 + bool "Enable x86 video driver support" + depends on X86 + default n + help + Turn on this option to enable a very simple driver which uses vesa + to discover the video mode and then provides a frame buffer for use + by U-Boot. diff --git a/include/configs/chromebook_link.h b/include/configs/chromebook_link.h index 318f1a8..e0bf309 100644 --- a/include/configs/chromebook_link.h +++ b/include/configs/chromebook_link.h @@ -39,7 +39,6 @@
#define CONFIG_X86_OPTION_ROM_FILE pci8086,0166.bin #define CONFIG_X86_OPTION_ROM_ADDR 0xfff90000 -#define CONFIG_VIDEO_X86
#define CONFIG_PCI_MEM_BUS 0xe0000000 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS