From: Enrico Leto enrico.leto@siemens.com
Get the memory region information from system controller to reduce the number of platform specific headers. We were aligned on NXP mek board implementation. This need at least 1 header per memory configuration.
Signed-off-by: Enrico Leto enrico.leto@siemens.com Signed-off-by: Heiko Schocher hs@denx.de ---
(no changes since v1)
board/siemens/capricorn/board.c | 34 ++++++++++++++++++++++++++++++ include/configs/capricorn-common.h | 4 +++- 2 files changed, 37 insertions(+), 1 deletion(-)
diff --git a/board/siemens/capricorn/board.c b/board/siemens/capricorn/board.c index decac63db3b..484e2707183 100644 --- a/board/siemens/capricorn/board.c +++ b/board/siemens/capricorn/board.c @@ -73,6 +73,40 @@ int board_early_init_f(void) return 0; }
+#ifndef CONFIG_XPL_BUILD +void board_mem_get_layout(u64 *phys_sdram_1_start, + u64 *phys_sdram_1_size, + u64 *phys_sdram_2_start, + u64 *phys_sdram_2_size) +{ + sc_faddr_t addr_start, addr_end; + sc_faddr_t sdram_1_size, sdram_2_size; + sc_err_t sc_err; + + sc_err = sc_rm_get_memreg_info(-1, 6, &addr_start, &addr_end); + if (sc_err == SC_ERR_NONE) { + if (addr_end < 0x100000000) { + /* only lower RAM available */ + sdram_1_size = (addr_end + 1) - PHYS_SDRAM_1; + sdram_2_size = 0; + } else { + /* lower RAM (2 GB) und upper RAM available */ + sdram_1_size = SZ_2G; + sdram_2_size = (addr_end + 1) - PHYS_SDRAM_2; + } + } else { + /* Get default in case it would fail */ + sdram_1_size = PHYS_SDRAM_1_SIZE; + sdram_2_size = PHYS_SDRAM_2_SIZE; + } + + *phys_sdram_1_start = PHYS_SDRAM_1; + *phys_sdram_1_size = sdram_1_size; + *phys_sdram_2_start = PHYS_SDRAM_2; + *phys_sdram_2_size = sdram_2_size; +} +#endif /* ! CONFIG_XPL_BUILD */ + #define ENET_PHY_RESET IMX_GPIO_NR(0, 3) #define ENET_TEST_1 IMX_GPIO_NR(0, 8) #define ENET_TEST_2 IMX_GPIO_NR(0, 9) diff --git a/include/configs/capricorn-common.h b/include/configs/capricorn-common.h index 1f61b2b6af6..4d95f3fd79b 100644 --- a/include/configs/capricorn-common.h +++ b/include/configs/capricorn-common.h @@ -95,7 +95,9 @@ #define CFG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_2 0x880000000 -/* DDR3 board total DDR is 1 GB */ +/* Set default values to the smallest DDR we have in capricorn modules + * Use it in case the system controller would return an error + */ #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1 GB */ #define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 GB */