Second .cfg file
[2/2] BDI .cfg for MPC8349EA-MDS-PB
; bdiGDB configuration file for MPC8349EA-MDS-PB board ;------------------------------------------------------------------ ; ; 2/14/2008 D. W. Hawkins (dwh@ovro.caltech.edu) ; ; The Freescale MPC8349E/EA PowerQUICC II PowerPC processor ; has two evaluation boards; ; ; * MPC8349E-MDS-PB ; - MPC8349E processor (v1.x silicon) ; - DDR1 memory ; - Micron Q-Flash. ; ; * MPC8349EA-MDS-PB ; - MPC8349EA processor (v3.x silicon) ; - DDR2 memory ; - Spansion Mirror-bit (S29GL) Flash. ; ; The DDR memory controller requires a different configuration ; for the two boards, and the programming algorithms for the ; Flash is different. ; ;------------------------------------------------------------------ ; NOTES: ; ------ ; ; 1. If the DDR memory is not known to be working (eg. on another ; MPC8349EA-based board), comment out the WORKSPACE used by ; the [FLASH] programming section below. ; ; 2. The memory map (local address window LAW) register settings ; in the [INIT] section were made identical to the ; U-Boot 1.3.1 settings (read from the board registers ; after U-Boot had started). ; ; 0x0000_0000 - 0x0FFF_FFFF 256MB DDR2 (single SODIMM) ; 0xE000_0000 - 0xE00F_FFFF 1MB IMMR ; 0xE240_0000 - 0xE240_7FFF 32kB BCSR ; 0xFE00_0000 - 0xFFFF_FFFF 32MB Flash ; ; Note that the BCSRs are located at 0xF800_0000 in the ; Freescale MPC8349EA-MDS-PB documentation. That documentation ; also defines PCI inbound/outbound windows. These windows ; are not configured by this configuration file, or by ; U-Boot 1.3.1. ; ; 3. U-Boot 1.3.1 uses low-memory boot, i.e., BMS = 0 in the ; reset configuration words. The DIP switch for FCFG ; (SW4.8) must be in the '1' position (closest to the ; power connector below it). This ensures that the RCWs ; are read from Flash. ; ; Once the Flash is programmed, the RCW entry in the ; [TARGET] section can be commented out. ; ; 4. In the MPC8349EA-MDS-PB schematic (Rev 2.0 Ver 0.2, 11/2006), ; the DDR DQS7 signal routes to DQS7 on U54.191 (the installed ; SODIMM), and DQS7# on U17.189 (the optional SODIMM). Given ; this error, its unlikely the second SODIMM is useable. ; ; 5. U-Boot 1.3.1 initial messages: ; ; CPU: e300c1, MPC8349E, Rev: 31 at 528 MHz, CSB: 264 MHz ; Board: Freescale MPC8349EMDS ; I2C: ready ; DRAM: 256 MB (DDR2, 64-bit, ECC on) ; FLASH: 32 MB ; In: serial ; Out: serial ; Err: serial ; Net: TSEC0, TSEC1 ; ; So the CPU operates at 528MHz, the DDR operates ; at 132MHz clock rate (264MHz data rate), DDR ECC is on. ; ;------------------------------------------------------------------ ; REFERENCES: ; ----------- ; ; [1] "MPC8349EA PowerQUICC II Pro Integrated Host Processor ; Family Reference Manual", Rev. 1 08/2006, Freescale ; Semiconductor (MPC8349EARM.pdf). ; ; [2] "MPC8349EA MDS Processor Board User Manual", Rev. 0.1, ; 12/2006, Freescale Semiconductor. ; ; [3] "HYB18T256400/800/160AF(L) 256Mbit DDR2 SDRAM", Rev 1.41, ; 1/2007, Qimonda. ; ;------------------------------------------------------------------ ; ; ================================================================= [INIT] ; init core register WREG MSR 0x00001002 ;MSR ME,RI
; Internal Memory Mapped Registers (IMMR) ; --------------------------------------- ; ; The base address of the 1MB of IMMR registers defaults ; to 0xFF40_0000 (see Ch. 2 and Ch. 5 [1]). ; ; Write to IMMRBAR to move the IMMRs to 0xE000_0000. ; WM32 0xFF400000 0xE0000000
; Local Address Windows (LAWs) ; ---------------------------- ; ; The processor has 9 LAWs (see Table 5-1 in Ch. 5 [1]). ; ; The MPC8349EA-MDS-PB uses; ; - a local-bus LAW for Flash ; - a local-bus LAW for BCSRs ; - a DDR LAW for DDR2 memory ; - and it can use a PCI LAW for PCI accesses ;
; Local-bus Flash ; --------------- ; LBC Local Access Window 0 Base Address Register (p5-7 [1]). ; LBLAWBAR0 ; [ 0:19] BASE_ADDR Base address MSBs (1MB aligned) ; [20:31] ----- Reserved ; ; LBC Local Access Window 0 Attributes Register (p5-8 [1]). ; LBLAWAR0 ; [0] EN Enabled (1) ; [26:31] SIZE Decode region is 2^(SIZE-1)-bytes ; WM32 0xE0000020 0xFE000000 ;LBLAWBAR0 Flash WM32 0xE0000024 0x80000018 ;LBLAWAR0 32MB
; Local-bus Board Control and Status Registers (BCSRs) ; ---------------------------------------------------- ; LBC Local Access Window 1 Base Address Register (p5-7 [1]). ; LBLAWBAR1 ; [ 0:19] BASE_ADDR Base address MSBs (1MB aligned) ; [20:31] ----- Reserved ; ; LBC Local Access Window 1 Attributes Register (p5-8 [1]). ; LBLAWAR1 ; [0] EN Enabled (1) ; [26:31] SIZE Decode region is 2^(SIZE-1)-bytes ; WM32 0xE0000028 0xE2400000 ;LBLAWBAR1 BCSR WM32 0xE000002C 0x8000000E ;LBLAWAR1 32kB
; DDR Memory ; ---------- ; DDR Local Access Window 0 Base Address Register (p5-12 [1]). ; DDRLAWBAR0 ; [ 0:19] BASE_ADDR Base address MSBs (1MB aligned) ; [20:31] ----- Reserved ; ; DDR Local Access Window 0 Attributes Register (p5-13 [1]). ; DDRLAWAR0 ; [0] EN Enabled (1) ; [26:31] SIZE Decode region is 2^(SIZE-1)-bytes ; WM32 0xE00000A0 0x00000000 ;DDRLAWBAR0 SODIMM#1 WM32 0xE00000A4 0x8000001B ;DDRLAWAR0 256MB
; DDR Driver Configuration ; ------------------------ ; ; DDR Control Driver Register (p5-28 [1]) ; DDRCDR ; [0] DHC_EN Driver hardware compensation enable ; [1] DSO_EN Driver software override enable ; [2:5] DSO_PZ Driver software p-impedance override ; [6:9] DSO_NZ Driver software n-impedance override ; [10] MDIC0_OE Software calibration MDIC0 output-enable ; [11] MDIC1_OE Software calibration MDIC1 output-enable ; [12] ODT ODT termination for IOs; 0 75-Ohm, 1 150-ohm ; [13] DDR_TYPE 0 DDR2 (1.8V mode), 1 DDR1 (2.5V mode) ; [14:30] --- Reserved ; [31] DRQ Drain queue before sleep ; ; Configure for; ; - hardware compensation ; - 150-Ohm ODT ; - DDR2 ; - drain queue before sleep. ; WM32 0xE0000128 0x80080001 ;DDRCDR
; DDR Clock Control ; ----------------- ; ; MCK Enable Register (p4-42 [1]) ; MCKENR ; [0] CE0 MCK[0]/MCK#[0] disable(0) / enable (1) ; [1] CE1 MCK[1]/MCK#[1] disable(0) / enable (1) ; [2] CE2 MCK[2]/MCK#[2] disable(0) / enable (1) ; [3] CE3 MCK[3]/MCK#[3] disable(0) / enable (1) ; [4] CE4 MCK[4]/MCK#[4] disable(0) / enable (1) ; [5] CE5 MCK[5]/MCK#[5] disable(0) / enable (1) ; ; The reset value for this register is 0xFC00_0000, ; i.e., all clocks enabled. The schematic shows that ; clocks 0 to 3 are used, whereas 4 and 5 route ; to test-points. These clocks can be disabled if ; desired. ; ;WM32 0xE0001010 0xF0000000 ;MCKENR
; DDR Clock Control (p9-28 [1]) ; ----------------- ; DDR_SDRAM_CLK_CNTL ; [0: 4] ---- Reserved ; [5: 8] CLK_ADJUST Clock adjust ; [9:31] ---- Reserved ; ; CLK_ADJUST resets to 0100b, so the clock is launched 1/2 ; a clock after the address/command. No change is required. ; ;WM32 0xE0002130 0x02000000 ;DDR_SDRAM_CLK_CNTL
; DDR Memory Controller ; --------------------- ; ; Chip-select n (0,1,2,3) memory bounds (p9-10 [1]) ; CSn_BNDS ; [ 0: 7] --- Reserved ; [ 8:15] SAn Start address for bank n ; [16:23] --- Reserved ; [34:31] EAn Start address for bank n ; ; The MPC8349EA-MDS-PB connects the four chip-selects ; (CS#[0:3]) to the two SODIMM modules. Only one SODIMM ; is populated by default (U54), so only the two chip ; selects used by that SODIMM need to be configured, ; i.e., CS#[2:3]. ; ; U-Boot 1.3.1 configures CS#[2] to decode the 256MB. ; ; Configure for; ; - Memory range: 0x0000_0000 - 0x0FFF_FFFF ; - Start/end addresses (8-MSBs of the memory addresses) ; SA = 0x00, EA = 0x0F ; WM32 0xE0002000 0x00000000 ;CS0_BNDS WM32 0xE0002008 0x00000000 ;CS1_BNDS WM32 0xE0002010 0x0000000F ;CS2_BNDS WM32 0xE0002018 0x00000000 ;CS3_BNDS
; Chip-select n (0,1,2,3) configuration (p9-11 [1]) ; CSn_CONFIG ; [0] CS_n_EN Chip-select enable ; [ 1: 7] ---- Reserved ; [8] AP_n_EN Auto-precharge enable ; [ 9:11] ODT_RD_CFG ODT configuration for reads ; [12] ---- Reserved ; [13:15] ODT_WR_CFG ODT configuration for writes ; [16:17] BA_BITS_CS_n Number of banks ; [18:20] ---- Reserved ; [21:23] ROW_BITS_CS_n Number of row bits ; [24:28] ---- Reserved ; [29:31] COL_BITS_CS_n Number of column bits ; ; Configure for; ; - CS#[0, 1, 3] disabled ; - CS#[2] configure for; ; CS_n_EN = 1b Enabled ; AP_n_EN = 0b Use global auto-precharge control ; ODT_RD_CFG = 000b Never assert for reads ; ODT_WR_CFG = 001b Assert only for writes to CS#[2] ; BA_BITS_CS_n = 00b 2 bank bits ; ROW_BITS_CS_n = 001b 13 row bits ; COL_BITS_CS_n = 010b 10 column bits ; WM32 0xE0002080 0x00000000 ;CS0_CONFIG WM32 0xE0002084 0x00000000 ;CS1_CONFIG WM32 0xE0002088 0x80010102 ;CS2_CONFIG WM32 0xE000208C 0x00000000 ;CS3_CONFIG
; Timing configuration (p9-13 [1]) ; TIMING_CFG_3 ; [ 0:12] ---- Reserved ; [13:15] EXT_REFREC Extended refresh recovery time ; [16:31] ---- Reserved ; ; The reset state of this register (0) is appropriate, ; so it does not need to be modified. ; ;WM32 0xE0002100 0x00000000 ;TIMING_CFG_3
; TIMING_CFG_0 (p9-14 [1]) ; [ 0: 1] RWT Read-to-write turn-around ; [ 2: 3] WRT Write-to-read turn-around ; [ 4: 5] RRT Read-to-read turn-around ; [ 6: 7] WWT Write-to-write turn-around ; [8] --- Reserved (should be 0) ; [ 9:11] ACT_PD_EXIT Active powerdown exit timing ; [12] --- Reserved (should be 0) ; [13:15] PRE_PD_EXIT Precharge powerdown exit timing ; [16:19] --- Reserved (should be 0) ; [20:23] ODT_PD_EXIT ODT powerdown exit timing ; [24:27] --- Reserved (should be 0) ; [28:31] MRS_CYC Mode register set cycle time ; ; Configure for; ; RWT = 00b 0 clocks ; WRT = 00b 0 clocks ; RRT = 00b 0 clocks ; WWT = 00b 0 clocks ; ACT_PD_EXIT = 010b 2 clocks ; PRE_PD_EXIT = 110b 6 clocks ; ODT_PD_EXIT = 1000b 8 clocks ; MRS_CYC = 0010b 2 clocks ; WM32 0xE0002104 0x00260802 ;TIMING_CFG_0
; TIMING_CFG_1 (p9-16 [1]) ; [0] ---- Reserved (should be 0) ; [ 1: 3] PRETOACT Precharge-to-activate ; [ 4: 7] ACTTOPRE Activate to precharge ; [8] ---- Reserved (should be 0) ; [ 9:11] ACTTORW Activate to read/write ; [12:15] CASLAT CAS latency from read ; [16:19] REFREC Refresh recovery time ; [20] ---- Reserved (should be 0) ; [21:23] WRREC Last data to precharge ; [24] ---- Reserved (should be 0) ; [25:27] ACTTOACT Activate-to-activate ; [28] ---- Reserved (should be 0) ; [29:31] WRTORD Last write to read ; ; Configure for; ; PRETOACT = 010b 2 clocks ; ACTTOPRE = 0110b 6 clocks ; ACTTORW = 010b 2 clocks ; CASLAT = 0111b 4 clocks ; REFREC = 0010b 10 clocks ; WRREC = 010b 2 clocks ; ACTTOACT = 001b 1 clock ; WRTORD = 010b 2 clocks ; WM32 0xE0002108 0x26272212 ;TIMING_CFG_1
; TIMING_CFG_2 (p9-18 [1]) ; [0] ---- Reserved ; [ 1: 3] ADD_ACT Additive latency ; [ 4: 8] CPO CAS-to-preamble override ; [9] ---- Reserved ; [10:12] WR_LAT Write latency ; [13:15] ---- Reserved ; [16:18] RD_TO_PRE Read-to-precharge ; [19:21] WR_DATA_DELAY Write command to write data ; [22] ---- Reserved ; [23:25] CKE_PLS Minimum CKE pulse width ; [26:31] FOUR_ACT Window for four activates ; ; Configure for; ; ADD_ACT = 000b 0 clocks ; CPO = 00111b RD_LAT + 5/4 ; WR_LAT = 011b 3 clocks ; RD_TO_PRE = 001b 1 clock ; WR_DATA_DELAY = 010b 1/2 clock delay ; CKE_PLS = 011b 3 clocks ; FOUR_ACT = 000101b 5 clocks ; WM32 0xE000210C 0x039828C5 ;TIMING_CFG_2
; DDR Control Configuration (p9-20 [1]) ; ------------------------------------- ; ; Disable the controller during configuration. ; ; DDR_SDRAM_CFG ; [0] MEM_EN DDR interface enable ; [1] SREN Self-refresh enable ; [2] ECC_EN ECC enable ; [3] RD_EN Registered DIMM enable ; [4] ---- Reserved ; [ 5: 7] SDRAM_TYPE Device type (010b DDR1, 011b DDR2) ; [ 8: 9] ---- Reserved ; [10] DYN_PWR Dynamic power management mode ; [11] ---- Reserved ; [12] 32_BE 32-bit bus enable ; [13] 8_BE 8-beat burst enable (DDR1 only) ; [14] NCAP Non-concurrent auto-precharge ; [15] ---- Reserved ; [16] 2T_EN Enable 2T timing ; [17:23] BA_INTLV_CTL Bank interleaving control ; [24:25] ---- Reserved ; [26] x32_EN x32 enable (32-bit chips are used) ; [27] PCHB8 Precharge bit 8 enable ; [28] HSE Global half-strength override ; [29] ---- Reserved ; [30] MEM_HALT Memory controller halt ; [31] BI Bypass initialization ; ; Configure for; ; MEM_EN = 0b Enabled ; SREN = 1b Self-refresh enabled (during sleep) ; ECC_EN = 0b ECC enabled ; RD_EN = 0b Unbuffered DIMM ; SDRAM_TYPE = 011b DDR2 SDRAM ; DYN_PWR = 0b Dynamic power management disabled ; 32_BE = 0b 64-bit bus ; 8_BE = 0b 4-beat bursts used ; NCAP = 0b DRAMs support concurrent precharge ; 2T_EN = 0b 1T timing is used ; BA_INTLV_CTL = 0000000b No external banks are interleaved ; x32_EN = 0b Either x8 or x16 chips are used ; PCHB8 = 0b MA[10] used to indicate precharge ; HSE = 0b Full-strength I/O drivers ; MEM_HALT = 0b Controller accepts new transactions ; BI = 0b Controller initializes the DDR based ; on SDRAM_TYPE setting ; WM32 0xE0002110 0x43000000 ;DDR_SDRAM_CFG
; DDR Control Configuration 2 (p9-22 [1]) ; --------------------------------------- ; DDR_SDRAM_CFG_2 ; [0] FRC_SR Force self-refresh ; [1] SR_IE Self-refresh interrupt enable ; [2] DLL_RST_DIS DLL reset disable ; [3] ---- Reserved ; [ 4: 5] DQS_CFG DQS Configuration ; [ 6: 8] ---- Reserved ; [ 9:10] ODT_CFG ODT configuration ; [11:15] ---- Reserved ; [16:19] NUM_PR Numer of posted refreshes ; [20:26] ---- Reserved (should be 0) ; [27] D_INIT DRAM data initialization ; [28:31] ---- Reserved ; ; Configure for; ; FRC_SR = 0b Operate in normal mode ; SR_IE = 0b Do not self-refresh if panic interrupt ; DLL_RST_DIS = 0b Issue DLL reset on self-refresh exit ; DQS_CFG = 00b Only true DQS signals are used ; ODT_CFG = 10b Assert ODT to internal IOs during reads ; NUM_PR = 0001b 1 refresh at a time ; D_INIT = 0b Data initialization complete ; WM32 0xE0002114 0x00401000 ;DDR_SDRAM_CFG_2
; DDR mode configuration (p9-24 [1]) ; ---------------------- ; DDR_SDRAM_MODE ; [ 0:15] ESDMODE Extended SDRAM mode ; [16:31] SDMODE SDRAM mode ; ; The mode settings are defined by the DDR memory manufacturer. ; ; The MPC8349EA-MDS-PB DDR2 SODIMM markings are: ; - WV3HG32M72EEU403PD4GG (which matches p25 [2]) ; - The modules have 9 pcs of 8-bit wide Qimonda HYB18T256800AF-5 ; 8-bit wide DDR2-400 devices (used to create a ; 64-bit + 8-bit ECC = 72-bit DDR module) ; ; Notes from the Qimonda data sheet [3]; ; - p5. HYB18T256800AF-5 CAS-RCD-RD = 3-3-3 ; - p14. 1K page size (10-bits column address) ; 32MB/1K = 32K (15-bits bank+row address) ; 2-bit bank, 13-bit row, 10-bit column addressing ; ; Mode Register (BA[1:0] = 00b) (p15 [3]) ; MODE ; [12] PD Active power-down mode select ; [11: 9] WR Write recovery ; [8] DLL DLL reset ; [7] TM Test mode ; [ 6: 4] CL CAL Latency ; [3] BT Burst type ; [ 2: 0] BL Burst length ; ; Extended mode 1 register (BA[1:0] = 01b) (p17 [3]) ; EXTMODE ; [12] QOFF Output buffers disable ; [11] RDQS Read data strobe output enable ; [10] DQS# Complimentary data strobe output enable ; [ 9: 7] OCD Off-chip driver calibration program ; [ 5: 3] AL Additive latency ; [ 6, 2] RTT Nominal termination resistance ; [1] DIC Off-chip driver impedance control ; [0] DLL DLL enable ; ; Extended mode 2 register (BA[1:0] = 10b) (p19 [3]) ; Extended mode 3 register (BA[1:0] = 11b) (p20 [3]) ; ; U-Boot 1.3.1 mode and extended mode settings: ; ; Configure the SDMODE register for; ; PD = 0b Fast exit ; WR = 001b WR 2 ; DLL = 0b DLL is not reset ; TM = 0b Normal mode ; CL = 100b CL 4 ; BT = 0b Sequential burst ; BL = 010b Burst length of 4 ; ; SDMODE = 0000_0010_0100_0010b = 0242h ; ; QOFF = 0b Output buffers enabled ; RDQS = 0b Read DQS output enabled ; DQS# = 1b Complimentary DQS disable ; OCD = 000b Exit calibration mode, maintain setting ; AL = 000b AL 0 ; RTT = 10b 150-Ohm termination ; DIC = 0b Full-strength drive ; DLL = 0b DLL enabled ; ; EXTMODE = 0000_0100_0100_0000b = 0440h ; ; The ESDMODE2 and ESDMODE3 registers are set to zero. ; WM32 0xE0002118 0x04400242 ;DDR_SDRAM_MODE WM32 0xE000211C 0x00000000 ;DDR_SDRAM_MODE_2
; DDR Interval Configuration (p9-27, p9-57 [1]) ; -------------------------- ; DDR_SDRAM_INTERVAL ; [ 0:15] REFINT Refresh interval ; [16:17] ---- ; [18:31] BSTOPRE Precharge interval ; ; Refresh interval: ; - DDR device requirement: tREFI = 7.81us (p48 [3]) ; - The DDR clocks operate at 132MHz (264MHz data rate) ; - Number of DDR clocks per tREFI: ; 132MHz x 7.81us = 1030 clocks (406h) ; - This matches the U-Boot setting ; - Technically the clock count should have the number of ; clocks for the longest possible transaction subtracted ; from this value (p9-57 [1]). ; ; Precharge interval ; - U-Boot has it as 100h, so 1.94us (about tREFI/4). ; - p9-62 discusses open-page mode, and p9-69 indicates ; that BSTOPRE can be set to any value. ; WM32 0xE0002124 0x04060100 ;DDR_SDRAM_INTERVAL
; Delay before enabling the DDR controller ; (p9-69 indicates at least a 200us delay is required) DELAY 300
; DDR Control Configuration (p9-20 [1]) ; ------------------------------------- ; ; This write enables the controller, so should occur after ; the other DDR registers are configured. ; ; DDR_SDRAM_CFG ; [0] MEM_EN DDR interface enable ; [1] SREN Self-refresh enable ; [2] ECC_EN ECC enable ; [3] RD_EN Registered DIMM enable ; [4] ---- Reserved ; [ 5: 7] SDRAM_TYPE Device type (010b DDR1, 011b DDR2) ; [ 8: 9] ---- Reserved ; [10] DYN_PWR Dynamic power management mode ; [11] ---- Reserved ; [12] 32_BE 32-bit bus enable ; [13] 8_BE 8-beat burst enable (DDR1 only) ; [14] NCAP Non-concurrent auto-precharge ; [15] ---- Reserved ; [16] 2T_EN Enable 2T timing ; [17:23] BA_INTLV_CTL Bank interleaving control ; [24:25] ---- Reserved ; [26] x32_EN x32 enable (32-bit chips are used) ; [27] PCHB8 Precharge bit 8 enable ; [28] HSE Global half-strength override ; [29] ---- Reserved ; [30] MEM_HALT Memory controller halt ; [31] BI Bypass initialization ; ; Configure for; ; MEM_EN = 1b Enabled ; SREN = 1b Self-refresh enabled (during sleep) ; ECC_EN = 1b ECC enabled ; RD_EN = 0b Unbuffered DIMM ; SDRAM_TYPE = 011b DDR2 SDRAM ; DYN_PWR = 0b Dynamic power management disabled ; 32_BE = 0b 64-bit bus ; 8_BE = 0b 4-beat bursts used ; NCAP = 0b DRAMs support concurrent precharge ; 2T_EN = 0b 1T timing is used ; BA_INTLV_CTL = 0000000b No external banks are interleaved ; x32_EN = 0b Either x8 or x16 chips are used ; PCHB8 = 0b MA[10] used to indicate precharge ; HSE = 0b Full-strength I/O drivers ; MEM_HALT = 0b Controller accepts new transactions ; BI = 0b Controller initializes the DDR based ; on SDRAM_TYPE setting ; WM32 0xE0002110 0xE3000000 ;DDR_SDRAM_CFG
; Local-bus Controller ; -------------------- ; ; Setup chip selects ; ; Base Register ; BRn ; [ 0:16] BA Base address (17-bits) ; [17:18] ---- Reserved ; [19:20] PS Port size ; [21:22] DECC Data ECC method ; [23] WP Write protect ; [24:26] MSEL Machine select (GPCM, SDRAM, UPM) ; [27:30] ---- Reserved ; [31] V Valid bit (BRn and ORn are valid) ; ; Options Register ; ORn ; [ 0:16] AM Address mask (defines the region size) ; [17:18] ---- Reserved ; [19] BCTLD Buffer control disable (LBCTL) ; [20] CSNT Chip-select negation time ; [21:22] ACS Address to chip-select setup ; [23] XACS Extra address to chip-select setup ; [24:27] SCY Cycle length in bus clocks ; [28] SETA External address termination ; [29] TRLX Timing relaxed ; [30] EHTR Extended hold time on read accesses ; [31] EAD External address latch delay ; ; The options register (ORn) should be set first, and ; then the base register (BRn), with the valid bit set. ; ; The reset state for 16-bit Flash boot is: ; BR0 = 0000_1001h ; BA = 0h Flash is at address 0h ; PS = 10b 16-bits ; DECC = 00b Data error checking disabled ; WP = 0b R/W allowed ; MSEL = 000b GPCM ; V = 1b Valid (enabled) ; ; OR0 = 0000_0FF7h ; AM = 0b 4GB decode ; BCTLD = 0b LBCTL asserts ; CSNT = 1b LCS#0 and LWE# assert 1/4 clock earlier ; ACS = 11b LCS#0 asserts half a clock after address ; XACS = 1b Address to chip select extended ; SCY = 1111b 15 clocks of wait-states ; SETA = 0b Internal termination ; TRLX = 1b Relaxing timing ; EHTR = 1b Extended hold on read accesses (8 clocks) ; EAD = 1b LALE asserted for 4 clocks ; ; The RCWs and local bus LAW reset settings generate an 8MB ; window located at address 0. ; ; The settings for the 32MB Spansion Flash located at ; FE00_0000h (the address window setup above) just modify ; the base address, and address mask fields to put the ; 32MB flash at the end of memory in a 32MB window. ; The access timing settings remain the same. ; WM32 0xE0005004 0xFE000FF7 ;OR0 : Flash WM32 0xE0005000 0xFE001001 ;BR0 : Flash WM32 0xE000500C 0xFFFFE8F0 ;OR1 : BCSR WM32 0xE0005008 0xE2400801 ;BR1 : BCSR
; Enable flash programming ; ------------------------ ; ; Write to the BCSR to deassert write-protect (WP# = 1) ; WM8 0xE2400001 0x0C
; ================================================================= [TARGET] CPUTYPE 8349 ;the CPU type JTAGCLOCK 0 ;use 16 MHz JTAG clock POWERUP 2000 ;start delay after power-up detected in ms WAKEUP 500 ;give reset time to complete STARTUP RESET ;halt immediately at the boot vector
; Reset Configuration Words (p4-11 [1]) ; ------------------------- ; ; The BDI2000 RCW command can be used to over-ride the RCWs. ; This is useful when the RCWs will be fetched from Flash, ; but the Flash is empty. ; ; The configuration of the RCWs can be done using the clock ; and reset tool (GUI) available on Freescale's web site. ; ; Reset Configuration Words Low Register ; --------------------------------------- ; RCWLR (p4-11 [1]) ; [0] LBIUCM Local bus interface unit clock mode ; [1] DDRCM DDR clock mode ; [ 2: 3] ---- Reserved ; [ 4: 7] SPMF System PLL multiplication factor ; [8] ---- Reserved ; [ 9:15] COREPLL Core PLL configuration ; [16:31] ---- Reserved ; ; Configure for 66MHz external clock; ; LBIUCM = 0b 1:1 Mode (lbc_clk = 264MHz) ; DDRCM = 0b 1:1 Mode (ddr_clk = 264MHz) ; SPMF = 0100b x4 (csb_clk = 264MHz = 66MHz x 4) ; COREPLL = 0000100b x2 (core_clk = 528MHz, VCO 1056MHz) ; ; Reset Configuration Words High Register ; --------------------------------------- ; RCWL (p4-14 [1]) ; [0] PCIHOST PCI host/agent mode ; [1] PCI64 PCI 64-bit mode ; [2] PCI1ARB PCI1 internal arbiter mode ; [3] PCI2ARB PCI2 internal arbiter mode ; [4] COREDIS Core disable mode ; [5] BMS Boot memory space ; [ 6: 7] BOOTSEQ Boot sequencer configuration ; [8] SWEN Software watchdog enable ; [ 9:11] ROMLOC Boot ROM interface location ; [12:15] ---- Reserved (should be 0) ; [16:17] TSEC1M TSEC1 mode ; [18:19] TSEC2M TSEC2 mode ; [20-27] ---- Reserved (should be 0) ; [28] TLE True little-endian ; [29] LALE Local bus LALE timing ; [30] LDP LDP pin mux state after reset ; [31] ---- Reserved (should be 0) ; ; Configure for host-mode, local-bus Flash low-memory boot; ; PCIHOST = 1b Host-mode ; PCI64 = 0b 32-bit (PCI1 and PCI2 enabled) ; PCI1ARB = 1b PCI1 arbiter enabled ; PCI2ARB = 1b PCI2 arbiter enabled ; COREDIS = 0b Core enabled ; BMS = 0b Low-memory boot ; BOOTSEQ = 00b Boot sequencer disabled ; SWEN = 0b Watchdog disabled ; ROMLOC = 110b 16-bit local bus GPCM ; TSEC1M = 10b GMII mode ; TSEC2M = 10b GMII mode ; TLE = 0b Big-endian mode ; LALE = 0b Normal timing ; LDP = 0b Local data parity ; ; Format: RCW RCWH RCWL ;RCW 0xB060A000 0x04040000
BOOTADDR 0x00000100 ;boot address used for start-up break BREAKMODE SOFT ;SOFT or HARD, HARD uses PPC hardware breakpoint STEPMODE HWBP ;TRACE or HWBP, HWBP uses a hardware breakpoint ;MMU XLAT 0xc0000000 ;enable address translation ;SIO 8023 115200
; ================================================================= [HOST] IP 192.168.17.61 ;FILE c:\temp\test.elf ;FORMAT ELF ;FILE c:\temp\dump512k.bin FORMAT BIN 0x10000 LOAD MANUAL ;load code MANUAL or AUTO after reset PROMPT 8349>
; ================================================================= [FLASH] CHIPTYPE MIRRORX16 ;Flash type: Spansion S29GL256N 32MB CHIPSIZE 0x2000000 ;The size of one flash chip in bytes BUSWIDTH 16 ;The width of the flash memory bus in bits ; (8 | 16 | 32 | 64) ;WORKSPACE 0x1000 ;workspace in DDR RAM FILE u-boot-1.3.1.bin FORMAT BIN 0xfe000000 ERASE 0xfe000000 ;erase sector 0 (128kB sectors) ERASE 0xfe020000 ;erase sector 1
; ================================================================= [REGS] FILE $reg8349e.def