When sd/mmc work at DDR mode, like HS400/HS400ES/DDR52/DDR50 mode, the output clock rate is half of the internal clock rate. But first need set DDR_EN bit first , then hardware will automatically divide the usdhc clock.
The mixctrl register exits on new i.MX SoC since i.MX6, so add CONFIG check.
Signed-off-by: Peng Fan peng.fan@nxp.com --- drivers/mmc/fsl_esdhc.c | 13 +++++++++++++ 1 file changed, 13 insertions(+)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 377b2673a3..acd6e08abb 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -625,6 +625,19 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock) int sdhc_clk = priv->sdhc_clk; uint clk;
+ /* + * For ddr mode, usdhc need to enable DDR mode first, + * after select this DDR mode, usdhc will automatically + * divide the usdhc clock + */ + if (CONFIG_IS_ENABLED(ARCH_MX6) || CONFIG_IS_ENABLED(ARCH_MX7) || + CONFIG_IS_ENABLED(ARCH_MX7ULP) || CONFIG_IS_ENABLED(ARCH_IMX8) || + CONFIG_IS_ENABLED(ARCH_IMX8M)) { + if (mmc->ddr_mode) + writel(readl(®s->mixctrl) | MIX_CTRL_DDREN, + ®s->mixctrl); + } + if (clock < mmc->cfg->f_min) clock = mmc->cfg->f_min;