From: Tien Fong Chee tien.fong.chee@intel.com
The system manager on Arria10 is not used for pin muxing duties, so wrap these functions for GEN5 devices only.
Signed-off-by: Dinh Nguyen dinguyen@opensource.altera.com Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com Cc: Marek Vasut marex@denx.de Cc: Dinh Nguyen dinguyen@kernel.org Cc: Chin Liang See chin.liang.see@intel.com Cc: Tien Fong skywindctf@gmail.com --- arch/arm/mach-socfpga/system_manager.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-socfpga/system_manager.c b/arch/arm/mach-socfpga/system_manager.c index 75a65f3..9e1c3fd 100644 --- a/arch/arm/mach-socfpga/system_manager.c +++ b/arch/arm/mach-socfpga/system_manager.c @@ -19,6 +19,7 @@ static struct socfpga_system_manager *sysmgr_regs = * The value is not wrote to SYSMGR.FPGAINTF.MODULE but * CONFIG_SYSMGR_ISWGRP_HANDOFF. */ +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) static void populate_sysmgr_fpgaintf_module(void) { uint32_t handoff_val = 0; @@ -83,3 +84,4 @@ void sysmgr_config_warmrstcfgio(int enable) clrbits_le32(&sysmgr_regs->romcodegrp_ctrl, SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO); } +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */