
7 Aug
2021
7 Aug
'21
10 a.m.
From: Ye Li ye.li@nxp.com
CMC1 also has a MR register for bootcfg
Signed-off-by: Ye Li ye.li@nxp.com --- arch/arm/mach-imx/imx8ulp/soc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index 6f4b506386..cddcdc2d20 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -23,7 +23,7 @@ enum bt_mode get_boot_mode(void) { u32 bt0_cfg = 0;
- bt0_cfg = readl(CMC0_RBASE + 0x80); + bt0_cfg = readl(CMC1_BASE_ADDR + 0xa0); bt0_cfg &= (BT0CFG_LPBOOT_MASK | BT0CFG_DUALBOOT_MASK);
if (!(bt0_cfg & BT0CFG_LPBOOT_MASK)) {
--
2.30.0