On 2022/7/30 07:49, Johan Jonker wrote:
Partial sync of rk3288.dtsi from Linux version 5.18
Changed: only properties and functions that are not yet included swap some clocks positions fix some irq numbers style and sort nodes
Signed-off-by: Johan Jonker jbx6244@gmail.com
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/dts/rk3288-veyron-jerry.dts | 6 - arch/arm/dts/rk3288-veyron.dtsi | 4 - arch/arm/dts/rk3288.dtsi | 368 ++++++++++++++++++++++----- 3 files changed, 304 insertions(+), 74 deletions(-)
diff --git a/arch/arm/dts/rk3288-veyron-jerry.dts b/arch/arm/dts/rk3288-veyron-jerry.dts index ff7669eb..40fee55c 100644 --- a/arch/arm/dts/rk3288-veyron-jerry.dts +++ b/arch/arm/dts/rk3288-veyron-jerry.dts @@ -137,12 +137,6 @@ }; };
- edp {
edp_hpd: edp_hpd {rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>;};- };
- emmc { /* Make sure eMMC is not in reset */ emmc_deassert_reset: emmc-deassert-reset {
diff --git a/arch/arm/dts/rk3288-veyron.dtsi b/arch/arm/dts/rk3288-veyron.dtsi index 4a9c27a4..35db8827 100644 --- a/arch/arm/dts/rk3288-veyron.dtsi +++ b/arch/arm/dts/rk3288-veyron.dtsi @@ -560,10 +560,6 @@ status = "okay"; };
-&hdmi_audio {
- status = "okay";
-};
- &gpu { status = "okay"; };
diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi index 6b03a63c..8c394c1e 100644 --- a/arch/arm/dts/rk3288.dtsi +++ b/arch/arm/dts/rk3288.dtsi @@ -15,6 +15,7 @@
interrupt-parent = <&gic>; aliases {
ethernet0 = &gmac;@@ -35,6 +36,15 @@ spi2 = &spi2; };
- arm-pmu {
compatible = "arm,cortex-a12-pmu";interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;- };
- cpus { #address-cells = <1>; #size-cells = <0>;
@@ -141,6 +151,26 @@ }; };
- reserved-memory {
#address-cells = <1>;#size-cells = <1>;ranges;/** The rk3288 cannot use the memory area above 0xfe000000* for dma operations for some reason. While there is* probably a better solution available somewhere, we* haven't found it yet and while devices with 2GB of ram* are not affected, this issue prevents 4GB from booting.* So to make these devices at least bootable, block* this area for the time being until the real solution* is found.*/dma-unusable@fe000000 {reg = <0xfe000000 0x1000000>;};- };
- xin24m: oscillator { compatible = "fixed-clock"; clock-frequency = <24000000>;
@@ -149,14 +179,22 @@ };
timer {
arm,use-physical-timer;
arm,cpu-registers-not-fw-configured;
always-on;
arm,no-tick-in-suspend;};
timer: timer@ff810000 {
compatible = "rockchip,rk3288-timer";reg = <0x0 0xff810000 0x0 0x20>;interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cru PCLK_TIMER>, <&xin24m>;clock-names = "pclk", "timer";};
display-subsystem {
@@ -164,51 +202,59 @@ ports = <&vopl_out>, <&vopb_out>; };
- sdmmc: dwmmc@ff0c0000 {
- sdmmc: mmc@ff0c0000 { compatible = "rockchip,rk3288-dw-mshc"; max-frequency = <150000000>; clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";resets = <&cru SRST_MMC0>;reset-names = "reset";
- sdio0: dwmmc@ff0d0000 {
- sdio0: mmc@ff0d0000 { compatible = "rockchip,rk3288-dw-mshc"; max-frequency = <150000000>; clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";resets = <&cru SRST_SDIO0>;reset-names = "reset";
- sdio1: dwmmc@ff0e0000 {
- sdio1: mmc@ff0e0000 { compatible = "rockchip,rk3288-dw-mshc"; max-frequency = <150000000>; clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>, <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";resets = <&cru SRST_SDIO1>;reset-names = "reset";
- emmc: dwmmc@ff0f0000 {
- emmc: mmc@ff0f0000 { compatible = "rockchip,rk3288-dw-mshc"; max-frequency = <150000000>; clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";resets = <&cru SRST_EMMC>;reset-names = "reset";@@ -219,6 +265,8 @@ #io-channel-cells = <1>; clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; clock-names = "saradc", "apb_pclk";
resets = <&cru SRST_SARADC>;reset-names = "saradc-apb";@@ -318,6 +366,7 @@ pinctrl-0 = <&i2c5_xfer>; status = "disabled"; };
- uart0: serial@ff180000 { compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; reg = <0xff180000 0x100>;
@@ -326,6 +375,8 @@ reg-io-width = <4>; clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; clock-names = "baudclk", "apb_pclk";
dmas = <&dmac_peri 1>, <&dmac_peri 2>;dma-names = "tx", "rx";@@ -339,6 +390,8 @@ reg-io-width = <4>; clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; clock-names = "baudclk", "apb_pclk";
dmas = <&dmac_peri 3>, <&dmac_peri 4>;dma-names = "tx", "rx";@@ -356,6 +409,7 @@ pinctrl-0 = <&uart2_xfer>; status = "disabled"; };
- uart3: serial@ff1b0000 { compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; reg = <0xff1b0000 0x100>;
@@ -364,6 +418,8 @@ reg-io-width = <4>; clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; clock-names = "baudclk", "apb_pclk";
dmas = <&dmac_peri 7>, <&dmac_peri 8>;dma-names = "tx", "rx";@@ -377,6 +433,8 @@ reg-io-width = <4>; clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; clock-names = "baudclk", "apb_pclk";
dmas = <&dmac_peri 9>, <&dmac_peri 10>;dma-names = "tx", "rx";@@ -388,7 +446,8 @@ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; #dma-cells = <1>;
broken-no-flushp;
arm,pl330-broken-no-flushp;arm,pl330-periph-burst;@@ -503,6 +562,8 @@ "mac_clk_rx", "mac_clk_tx", "clk_mac_ref", "clk_mac_refout", "aclk_mac", "pclk_mac";
resets = <&cru SRST_MAC>;reset-names = "stmmaceth";};
usb_host0_ehci: usb@ff500000 {
@@ -516,7 +577,7 @@ status = "disabled"; };
- /* NOTE: doesn't work on RK3288, but fixed on RK3288W */
- /* NOTE: doesn't work on RK3288, but was fixed on RK3288W */ usb_host0_ohci: usb@ff520000 { compatible = "generic-ohci"; reg = <0x0 0xff520000 0x0 0x100>;
@@ -534,8 +595,10 @@ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru HCLK_USBHOST1>; clock-names = "otg";
dr_mode = "host";snps,reset-phy-on-wake;@@ -547,6 +610,9 @@ clocks = <&cru HCLK_OTG0>; clock-names = "otg"; dr_mode = "otg";
g-np-tx-fifo-size = <16>;g-rx-fifo-size = <275>;g-tx-fifo-size = <256 128 128 64 64 32>;@@ -567,7 +633,8 @@ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; #dma-cells = <1>;
broken-no-flushp;
arm,pl330-broken-no-flushp;arm,pl330-periph-burst;@@ -647,7 +714,7 @@ status = "disabled"; };
- bus_intmem: bus_intmem@ff700000 {
- bus_intmem: sram@ff700000 { compatible = "mmio-sram"; reg = <0xff700000 0x18000>; #address-cells = <1>;
@@ -659,7 +726,7 @@ }; };
- sram@ff720000 {
- pmu_sram: sram@ff720000 { compatible = "rockchip,rk3288-pmu-sram", "mmio-sram"; reg = <0xff720000 0x1000>; };
@@ -701,7 +768,7 @@ compatible = "rockchip,rk3288-wdt", "snps,dw-wdt"; reg = <0xff800000 0x100>; clocks = <&cru PCLK_WDT>;
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;@@ -709,11 +776,11 @@ compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif"; reg = <0xff8b0000 0x10000>; #sound-dai-cells = <0>;
clock-names = "hclk", "mclk";clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
clocks = <&cru SCLK_SPDIF8CH>, <&cru HCLK_SPDIF8CH>;clock-names = "mclk", "hclk";
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;@@ -723,50 +790,97 @@ i2s: i2s@ff890000 { compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s"; reg = <0xff890000 0x10000>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;#address-cells = <1>;#size-cells = <0>;#sound-dai-cells = <1>;
#sound-dai-cells = <0>;interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>;clock-names = "i2s_clk", "i2s_hclk";
clock-names = "i2s_hclk", "i2s_clk";clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
rockchip,playback-channels = <8>;rockchip,capture-channels = <2>;status = "disabled";};
crypto: crypto@ff8a0000 {
compatible = "rockchip,rk3288-crypto";reg = <0xff8a0000 0x4000>;interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>,<&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>;clock-names = "aclk", "hclk", "sclk", "apb_pclk";resets = <&cru SRST_CRYPTO>;reset-names = "crypto-rst";};
iep_mmu: iommu@ff900800 {
compatible = "rockchip,iommu";reg = <0xff900800 0x40>;interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;clock-names = "aclk", "iface";#iommu-cells = <0>;status = "disabled"; };
isp_mmu: iommu@ff914000 {
compatible = "rockchip,iommu";reg = <0xff914000 0x100>, <0xff915000 0x100>;interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;clock-names = "aclk", "iface";#iommu-cells = <0>;rockchip,disable-mmu-reset;status = "disabled";};
rga: rga@ff920000 {
compatible = "rockchip,rk3288-rga";reg = <0xff920000 0x180>;interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;clock-names = "aclk", "hclk", "sclk";power-domains = <&power RK3288_PD_VIO>;resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>;reset-names = "core", "axi", "ahb";};
vopb: vop@ff930000 { compatible = "rockchip,rk3288-vop"; reg = <0xff930000 0x19c>; interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
power-domains = <&power RK3288_PD_VIO>;resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>; reset-names = "axi", "ahb", "dclk"; iommus = <&vopb_mmu>;
power-domains = <&power RK3288_PD_VIO>;
- vopb_out: port { #address-cells = <1>; #size-cells = <0>;
vopb_out_edp: endpoint@0 { reg = <0>; remote-endpoint = <&edp_in_vopb>; };vopb_out_hdmi: endpoint@1 { reg = <1>; remote-endpoint = <&hdmi_in_vopb>; };vopb_out_lvds: endpoint@2 { reg = <2>; remote-endpoint = <&lvds_in_vopb>; };vopb_out_mipi: endpoint@3 { reg = <3>; remote-endpoint = <&mipi_in_vopb>; };
- }; };
@@ -774,7 +888,8 @@ compatible = "rockchip,iommu"; reg = <0xff930300 0x100>; interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vopb_mmu";
clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;clock-names = "aclk", "iface";@@ -786,31 +901,35 @@ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
power-domains = <&power RK3288_PD_VIO>;
power-domains = <&power RK3288_PD_VIO>;
- vopl_out: port { #address-cells = <1>; #size-cells = <0>;
vopl_out_edp: endpoint@0 { reg = <0>; remote-endpoint = <&edp_in_vopl>; };vopl_out_hdmi: endpoint@1 { reg = <1>; remote-endpoint = <&hdmi_in_vopl>; };vopl_out_lvds: endpoint@2 { reg = <2>; remote-endpoint = <&lvds_in_vopl>; };vopl_out_mipi: endpoint@3 { reg = <3>; remote-endpoint = <&mipi_in_vopl>; };
- }; };
@@ -818,7 +937,8 @@ compatible = "rockchip,iommu"; reg = <0xff940300 0x100>; interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vopl_mmu";
clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;clock-names = "aclk", "iface";@@ -827,16 +947,14 @@ mipi_dsi: mipi@ff960000 { compatible = "rockchip,rk3288_mipi_dsi"; reg = <0xff960000 0x4000>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
/*pinctrl-names = "default";pinctrl-0 = <&lcdc0_ctl>;*/
power-domains = <&power RK3288_PD_VIO>;
#address-cells = <1>;#size-cells = <0>;
- ports {
reg = <1>; mipi_in: port { #address-cells = <1>; #size-cells = <0>;@@ -858,16 +976,21 @@ clocks = <&cru PCLK_LVDS_PHY>; clock-names = "pclk_lvds"; pinctrl-names = "default";
pinctrl-0 = <&lcdc0_ctl>;
pinctrl-0 = <&lcdc_ctl>;power-domains = <&power RK3288_PD_VIO>;- ports { #address-cells = <1>; #size-cells = <0>;
lvds_in: port@0 { reg = <0>;#address-cells = <1>; #size-cells = <0>;lvds_in_vopb: endpoint@0 { reg = <0>; remote-endpoint = <&vopb_out_lvds>;@@ -885,12 +1008,13 @@ reg = <0xff970000 0x4000>; interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>;
rockchip,grf = <&grf>;resets = <&cru 111>;
resets = <&cru SRST_EDP>;rockchip,grf = <&grf>;- ports { edp_in: port { #address-cells = <1>;
@@ -911,12 +1035,14 @@ compatible = "rockchip,rk3288-dw-hdmi"; reg = <0xff980000 0x20000>; reg-io-width = <4>;
ddc-i2c-bus = <&i2c5>;
#sound-dai-cells = <0>;power-domains = <&power RK3288_PD_VIO>;- ports { hdmi_in: port { #address-cells = <1>;
@@ -933,31 +1059,36 @@ }; };
- hdmi_audio: hdmi_audio {
compatible = "rockchip,rk3288-hdmi-audio";i2s-controller = <&i2s>;status = "disable";- };
- vpu: video-codec@ff9a0000 { compatible = "rockchip,rk3288-vpu"; reg = <0xff9a0000 0x800>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "aclk_vcodec", "hclk_vcodec";power-domains = <&power RK3288_PD_VIDEO>;
clock-names = "aclk", "hclk";iommus = <&vpu_mmu>;
power-domains = <&power RK3288_PD_VIDEO>;};
vpu_mmu: iommu@ff9a0800 { compatible = "rockchip,iommu"; reg = <0xff9a0800 0x100>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vpu_mmu";
clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;clock-names = "aclk", "iface";#iommu-cells = <0>;power-domains = <&power RK3288_PD_VIDEO>;
};
hevc_mmu: iommu@ff9c0440 {
compatible = "rockchip,iommu";reg = <0xff9c0440 0x40>, <0xff9c0480 0x40>;interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>;clock-names = "aclk", "iface";#iommu-cells = <0>;
status = "disabled";};
gpu: gpu@ffa30000 {
@@ -999,13 +1130,84 @@ }; };
- qos_gpu_r: qos@ffaa0000 {
compatible = "rockchip,rk3288-qos", "syscon";reg = <0xffaa0000 0x20>;- };
- qos_gpu_w: qos@ffaa0080 {
compatible = "rockchip,rk3288-qos", "syscon";reg = <0xffaa0080 0x20>;- };
- qos_vio1_vop: qos@ffad0000 {
compatible = "rockchip,rk3288-qos", "syscon";reg = <0xffad0000 0x20>;- };
- qos_vio1_isp_w0: qos@ffad0100 {
compatible = "rockchip,rk3288-qos", "syscon";reg = <0xffad0100 0x20>;- };
- qos_vio1_isp_w1: qos@ffad0180 {
compatible = "rockchip,rk3288-qos", "syscon";reg = <0x0 0xffad0180 0x0 0x20>;- };
- qos_vio0_vop: qos@ffad0400 {
compatible = "rockchip,rk3288-qos", "syscon";reg = <0x0 0xffad0400 0x0 0x20>;- };
- qos_vio0_vip: qos@ffad0480 {
compatible = "rockchip,rk3288-qos", "syscon";reg = <0xffad0480 0x20>;- };
- qos_vio0_iep: qos@ffad0500 {
compatible = "rockchip,rk3288-qos", "syscon";reg = <0xffad0500 0x20>;- };
- qos_vio2_rga_r: qos@ffad0800 {
compatible = "rockchip,rk3288-qos", "syscon";reg = <0xffad0800 0x20>;- };
- qos_vio2_rga_w: qos@ffad0880 {
compatible = "rockchip,rk3288-qos", "syscon";reg = <0xffad0880 0x20>;- };
- qos_vio1_isp_r: qos@ffad0900 {
compatible = "rockchip,rk3288-qos", "syscon";reg = <0xffad0900 0x20>;- };
- qos_video: qos@ffae0000 {
compatible = "rockchip,rk3288-qos", "syscon";reg = <0xffae0000 0x20>;- };
- qos_hevc_r: qos@ffaf0000 {
compatible = "rockchip,rk3288-qos", "syscon";reg = <0xffaf0000 0x20>;- };
- qos_hevc_w: qos@ffaf0080 {
compatible = "rockchip,rk3288-qos", "syscon";reg = <0xffaf0080 0x20>;- };
- dmac_bus_s: dma-controller@ffb20000 { compatible = "arm,pl330", "arm,primecell"; reg = <0xffb20000 0x4000>; interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; #dma-cells = <1>;
broken-no-flushp;
arm,pl330-broken-no-flushp;arm,pl330-periph-burst;@@ -1013,7 +1215,17 @@ efuse: efuse@ffb40000 { compatible = "rockchip,rk3288-efuse"; reg = <0xffb40000 0x10000>;
status = "disabled";
#address-cells = <1>;#size-cells = <1>;clocks = <&cru PCLK_EFUSE256>;clock-names = "pclk_efuse";cpu_id: cpu-id@7 {reg = <0x07 0x10>;};cpu_leakage: cpu_leakage@17 {reg = <0x17 0x1>;};};
gic: interrupt-controller@ffc01000 {
@@ -1072,7 +1284,7 @@
gpio0: gpio0@ff750000 { compatible = "rockchip,gpio-bank";
reg = <0xff750000 0x100>;
reg = <0xff750000 0x100>; interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru PCLK_GPIO0>;@@ -1191,6 +1403,24 @@ hdmi_cec_c0: hdmi-cec-c0 { rockchip,pins = <7 RK_PC0 2 &pcfg_pull_none>; };
hdmi_cec_c7: hdmi-cec-c7 {rockchip,pins = <7 RK_PC7 4 &pcfg_pull_none>;};hdmi_ddc: hdmi-ddc {rockchip,pins = <7 RK_PC3 2 &pcfg_pull_none>,<7 RK_PC4 2 &pcfg_pull_none>;};hdmi_ddc_unwedge: hdmi-ddc-unwedge {rockchip,pins = <7 RK_PC3 RK_FUNC_GPIO &pcfg_output_low>,<7 RK_PC4 2 &pcfg_pull_none>;};};pcfg_output_low: pcfg-output-low {output-low;};
pcfg_pull_up: pcfg-pull-up {
@@ -1210,7 +1440,7 @@ drive-strength = <12>; };
sleep {
suspend { global_pwroff: global-pwroff { rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>; };@@ -1228,6 +1458,12 @@ }; };
edp {edp_hpd: edp-hpd {rockchip,pins = <7 RK_PB3 2 &pcfg_pull_down>;};};- i2c0 { i2c0_xfer: i2c0-xfer { rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>,
@@ -1281,8 +1517,8 @@ }; };
lcdc0 {lcdc0_ctl: lcdc0-ctl {
lcdc {lcdc_ctl: lcdc-ctl { rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>, <1 RK_PD1 1 &pcfg_pull_none>, <1 RK_PD2 1 &pcfg_pull_none>,@@ -1299,7 +1535,7 @@ rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up>; };
sdmmc_cd: sdmcc-cd {
sdmmc_cd: sdmmc-cd { rockchip,pins = <6 RK_PC6 1 &pcfg_pull_up>; };@@ -1490,7 +1726,7 @@ };
uart0_cts: uart0-cts {
rockchip,pins = <4 RK_PC2 1 &pcfg_pull_none>;
rockchip,pins = <4 RK_PC2 1 &pcfg_pull_up>; }; uart0_rts: uart0-rts {@@ -1505,7 +1741,7 @@ };
uart1_cts: uart1-cts {
rockchip,pins = <5 RK_PB2 1 &pcfg_pull_none>;
rockchip,pins = <5 RK_PB2 1 &pcfg_pull_up>; }; uart1_rts: uart1-rts {@@ -1528,7 +1764,7 @@ };
uart3_cts: uart3-cts {
rockchip,pins = <7 RK_PB1 1 &pcfg_pull_none>;
rockchip,pins = <7 RK_PB1 1 &pcfg_pull_up>; }; uart3_rts: uart3-rts {@@ -1538,20 +1774,24 @@
uart4 { uart4_xfer: uart4-xfer {
rockchip,pins = <5 RK_PB4 3 &pcfg_pull_up>,<5 RK_PB5 3 &pcfg_pull_none>;
rockchip,pins = <5 RK_PB7 3 &pcfg_pull_up>,<5 RK_PB6 3 &pcfg_pull_none>; }; uart4_cts: uart4-cts {
rockchip,pins = <5 RK_PB6 3 &pcfg_pull_none>;
rockchip,pins = <5 RK_PB4 3 &pcfg_pull_up>; }; uart4_rts: uart4-rts {
rockchip,pins = <5 RK_PB7 3 &pcfg_pull_none>;
rockchip,pins = <5 RK_PB5 3 &pcfg_pull_none>; };};
tsadc {
otp_pin: otp-pin {rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;};otp_out: otp-out { rockchip,pins = <0 RK_PB2 1 &pcfg_pull_none>; };