The eNET uses the sc520 software timers rather than the PC/AT clones
Set all interrupts and timers up to be PC/AT compatible --- board/eNET/eNET.c | 38 ++++++++++++++++++++++++++++++++++++++ 1 files changed, 38 insertions(+), 0 deletions(-)
diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c index 9d782f3..ac3f958 100644 --- a/board/eNET/eNET.c +++ b/board/eNET/eNET.c @@ -185,3 +185,41 @@ int board_eth_init(bd_t *bis) eth_init(bis);
return adapters; + +void setup_pcat_compatibility() +{ + /* disable global interrupt mode */ + writeb(0x40, &sc520_mmcr->picicr); + + /* set all irqs to edge */ + writeb(0x00, &sc520_mmcr->pic_mode[0]); + writeb(0x00, &sc520_mmcr->pic_mode[1]); + writeb(0x00, &sc520_mmcr->pic_mode[2]); + + /* + * active low polarity on PIC interrupt pins, + * active high polarity on all other irq pins + */ + writew(0x0000,&sc520_mmcr->intpinpol); + + /* Set PIT 0 -> IRQ0, RTC -> IRQ8, FP error -> IRQ13 */ + writeb(SC520_IRQ0, &sc520_mmcr->pit_int_map[0]); + writeb(SC520_IRQ8, &sc520_mmcr->rtcmap); + writeb(SC520_IRQ13, &sc520_mmcr->ferrmap); + + /* Disable all other interrupt sources */ + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[0]); + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[1]); + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[2]); + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pit_int_map[1]); + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pit_int_map[2]); + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[0]); /* disable PCI INT A */ + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[1]); /* disable PCI INT B */ + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[2]); /* disable PCI INT C */ + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[3]); /* disable PCI INT D */ + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->dmabcintmap); /* disable DMA INT */ + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->ssimap); + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wdtmap); + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wpvmap); + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->icemap); +}