On 04/17/2012 03:36 PM, Simon Glass wrote:
Hi Scott,
On Tue, Apr 17, 2012 at 1:31 PM, Scott Wood scottwood@freescale.com wrote:
On 04/17/2012 03:18 PM, Simon Glass wrote:
On Tue, Apr 17, 2012 at 12:06 PM, Scott Wood scottwood@freescale.com wrote:
Doesn't the number of cells depend on the GPIO controller binding?
Yes, but this is the binding Tegra uses.
Still, it doesn't belong in the NAND binding. Maybe a future chip wants to use this NAND binding but a different GPIO binding. If nothing else, people tend to copy-and-paste such descriptions. We've still got people adding bindings for Freescale devices saying interrupts are encoded as a pair of cells, even though the interrupt controller now uses four cells per interrupt.
OK I see - are you are saying that we should just say something like:
"nvidia,wp-gpios : GPIO of write-protect line, as defined by gpio bindings"
Yes. If there were more than one GPIO line, you'd specify which one is which, similar to reg and interrupts.
-Scott