With recent CONFIG_TEXT_BASE changes, there are inconsistencies between several settings.
Adjust CONFIG_SYS_MONITOR_LEN to allow more code space. Move the MRC cache out of the way too.
Signed-off-by: Simon Glass sjg@chromium.org Fixes: e23cae30801 ("x86: som-db5800-som-6867: Adjust CONFIG_TEXT_BASE") ---
Changes in v3: - Add new patch
arch/x86/dts/baytrail_som-db5800-som-6867.dts | 2 +- configs/som-db5800-som-6867_defconfig | 1 + 2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/x86/dts/baytrail_som-db5800-som-6867.dts b/arch/x86/dts/baytrail_som-db5800-som-6867.dts index e9b56de7927b..ca7d97f2d48b 100644 --- a/arch/x86/dts/baytrail_som-db5800-som-6867.dts +++ b/arch/x86/dts/baytrail_som-db5800-som-6867.dts @@ -206,7 +206,7 @@ memory-map = <0xff800000 0x00800000>; rw-mrc-cache { label = "rw-mrc-cache"; - reg = <0x006f0000 0x00010000>; + reg = <0x005f0000 0x00010000>; }; }; }; diff --git a/configs/som-db5800-som-6867_defconfig b/configs/som-db5800-som-6867_defconfig index c4752a2b0a5c..73813500fa11 100644 --- a/configs/som-db5800-som-6867_defconfig +++ b/configs/som-db5800-som-6867_defconfig @@ -15,6 +15,7 @@ CONFIG_HAVE_VGA_BIOS=y CONFIG_GENERATE_PIRQ_TABLE=y CONFIG_GENERATE_MP_TABLE=y CONFIG_SEABIOS=y +CONFIG_SYS_MONITOR_LEN=2097152 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_BOOTSTAGE=y