This series introduces support for initialising & maintaining L2 caches on MIPS systems. This allows U-Boot to function correctly on systems where such caches are present, whereas without performing L2 maintenance it is likely to fail with cache coherence issues when writing code or performing DMA transfers. It also fixes up a few issues with the cache code in general, in particular ensuring that it clears execution hazards at appropriate points.
Paul Burton (14): board_f: Add a mach_cpu_init callback MIPS: ath79: Use mach_cpu_init instead of arch_cpu_init MIPS: Probe cache line sizes once during boot MIPS: Enable use of the instruction cache earlier MIPS: Preserve Config implementation-defined bits MIPS: If we don't need DDR for cache init, init cache first MIPS: Define register names for cache init MIPS: Map CM Global Control Registers MIPS: L2 cache support MIPS: Join the coherent domain when a CM is present MIPS: Malta: Enable CM & L2 support MIPS: Ensure Config.K0=2 applies before any memory accesses MIPS: Clear hazard between TagLo writes & cache ops MIPS: Ensure cache ops complete in mips_cache_reset
arch/mips/Kconfig | 24 ++++ arch/mips/cpu/Makefile | 2 + arch/mips/cpu/cm_init.S | 45 ++++++ arch/mips/cpu/cpu.c | 7 + arch/mips/cpu/start.S | 27 ++-- arch/mips/include/asm/cache.h | 9 ++ arch/mips/include/asm/cm.h | 62 +++++++++ arch/mips/include/asm/global_data.h | 7 + arch/mips/include/asm/mipsregs.h | 6 + arch/mips/lib/cache.c | 101 +++++++++++--- arch/mips/lib/cache_init.S | 271 +++++++++++++++++++++++++++++++++--- arch/mips/mach-ath79/cpu.c | 2 +- board/imgtec/malta/lowlevel_init.S | 6 - common/board_f.c | 6 + 14 files changed, 522 insertions(+), 53 deletions(-) create mode 100644 arch/mips/cpu/cm_init.S create mode 100644 arch/mips/include/asm/cm.h