Hi
The reason this works on the MPC826xADS boards is that this is only necessary to do when the 60x bus is in 60x mode. When the bus is in "Single PowerQUICC II bus mode" (BCR register bit 0 (EBM) = 0), the value driven on the bus when writing to ramaddr after the mode set command, comes from the PSDMR register.
All the 826xADS boards defaults to single 8260 mode bus. (no external cache and multiplexers)
-----Original Message----- From: Holger Speck [mailto:hospe@gmx.de] Sent: Tuesday, July 22, 2003 03:46 To: u-boot-users@lists.sourceforge.net Subject: [U-Boot-Users] MPC8260/66: SDRAM init
Hello,
I had some problems with the initialisation of SDRAM (64MB) on 60x bus. Below the code I changed according to MPC8260 UM/D:
memctl->memc_psdmr = psdmr | 0x18000000; /* Mode Register write */ /* see 11.4.9 SDRAM MODE-SET Command Timming MPC8260 UM/D 05/2003, REV 1 */ /* send mode (CAS latency as in PSDMR and burst length for 16- or 64-bit ports) to SDRAM */ ramaddr = (uchar *) (CFG_SDRAM_BASE | (((cas_latency << 4) | 0x2) << 3)); *ramaddr = c;
The original code does not set "ramaddr" to the mode value. I tested this new code on special board derived from the MPC8260ADS. I'm a litte bit astonished that the original code works on the MPC8260ADS.
Grettings, Holger
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