On Mon, 21 Jul 2014 19:51:50 +0100 Ian Campbell ijc@hellion.org.uk wrote:
On Fri, 2014-07-18 at 19:22 +0300, Siarhei Siamashka wrote:
Before driving the CKE pin (Clock Enable) high, the DDR3 spec requires to wait for additional 500 us after the RESET pin is de-asserted.
The DRAM controller takes care of this delay by itself, using a configurable counter in the SDR_IDCR register. This works in the same way on sun4i/sun5i/sun7i hardware (even the default register value 0x00c80064 is identical). Except that the counter is ticking a bit slower on sun7i (3 DRAM clock cycles instead of 2), resulting in longer actual delays for the same settings.
This patch keeps the old code and only removes the CONFIG_SUN7I ifdef. But maybe we should drop all of this and just add 'udelay(500)' after the DDR3 reset without bothering to play with these undocumented registers.
I'm happy to go with whichever you think is better.
If the total DRAM initialization time in u-boot is not really critical (all the delays are only fractions of millisecond), then I would probably go with the "cargo cult" approach and actually apply the delays in both places ('udelay(500)' after the DDR3 reset and keep the maximum delay in the SDR_IDCR register too).
I just feel uneasy about using only the SDR_IDCR approach, because it implies the 524MHz DRAM clock speed limit for sun4i/sun5i hardware if we don't want to violate the DDR3 requirements. And we would prefer to have at least the 528MHz clock speed option (the Allwinner A13 manual says that 533MHz is the DRAM clock limit for it).
The changes in the SDR_IDCR delay counter on sun7i hardware (which permit longer delays) are very interesting. It might be a hint that the DRAM controller in sun7i had been originally intended to support higher clock speeds than its predecessors. However the Allwinner A20 manual only advertises the 400MHz DRAM clock. It might be that the Allwinner engineers could not figure out how to configure the DRAM parameters to reach really high clock speeds and decided to be modest about this. However that's just a speculation on my side.
Anyway, if anybody has a logic analyzer (the hardware companies like Olimex and CubieTech?), then checking and confirming the timings between the signals on the CKE and RESET pins during the DRAM initialization would be very interesting to confirm that everything is alright.
Another interesting observation is that the u-boot-sunxi code (derived from the Allwinner boot0) did not configure the SDR_IDCR register for sun4i/sun5i, but performed the DDR3 reset very early. Possibly resulting in a sufficient time gap between the DDR3 reset and the DDR3 initialization steps.
Signed-off-by: Siarhei Siamashka siarhei.siamashka@gmail.com
Acked-by: Ian Campbell ijc@hellion.org.uk
Thanks.