20 Feb
2009
20 Feb
'09
4:23 p.m.
On Tue, 17 Feb 2009 20:25:03 +0100 Joakim Tjernlund Joakim.Tjernlund@transmode.se wrote:
The spd code for mpc83xx is so broken it isn't funny. This is what I
had
to do to get my Micron MT47H64M16-3. This isn't against current u-boot, but it is a
start.
well it applies, but it also nuked the first board I tried it on. For any new ddr work on 83xx, I'd suggest starting with porting the new common mpc8xxx ddr code.
Guys, I have a hard time figuring out the clk adjust, cpo, wrdata delay and 2T parameters to the DDR2 controller. How do I calculate these?
Also, how does the NUM_PR setting relate to Tras?
Jocke