diff -purN -x CVS u-boot-20040130cvs-dk1xxx_split_conf/board/altera/dk1s10/dk1s10.c u-boot-20040130cvs-dk1s10_mtx_ldk_20/board/altera/dk1s10/dk1s10.c --- u-boot-20040130cvs-dk1xxx_split_conf/board/altera/dk1s10/dk1s10.c 2004-02-01 00:49:06.000000000 +0100 +++ u-boot-20040130cvs-dk1s10_mtx_ldk_20/board/altera/dk1s10/dk1s10.c 2004-02-01 01:06:04.000000000 +0100 @@ -43,6 +43,14 @@ int board_early_init_f (void) int checkboard (void) { puts ("Board: Altera Nios 1S10 Development Kit\n"); +#if defined(CONFIG_NIOS_SAFE_32) + puts ("Conf.: Altera Safe 32 (safe_32)\n"); +#elif defined(CONFIG_NIOS_STANDARD_32) + puts ("Conf.: Altera Standard 32 (standard_32)\n"); +#elif defined(CONFIG_NIOS_MTX_LDK_20) + puts ("Conf.: Microtronix LDK 2.0 (LDK2)\n"); +#endif + return 0; } diff -purN -x CVS u-boot-20040130cvs-dk1xxx_split_conf/board/altera/dk1s10/vectors.S u-boot-20040130cvs-dk1s10_mtx_ldk_20/board/altera/dk1s10/vectors.S --- u-boot-20040130cvs-dk1xxx_split_conf/board/altera/dk1s10/vectors.S 2004-01-03 20:43:48.000000000 +0100 +++ u-boot-20040130cvs-dk1s10_mtx_ldk_20/board/altera/dk1s10/vectors.S 2004-02-01 01:06:04.000000000 +0100 @@ -1,6 +1,7 @@ /* * (C) Copyright 2003, Psyent Corporation * Scott McNutt + * Stephan Linz * * See file CREDITS for list of people who contributed to this * project. @@ -21,6 +22,8 @@ * MA 02111-1307 USA */ +#include + /************************************************************************* * Exception Vector Table @@ -55,8 +58,14 @@ .align 4 _vectors: - .long _def_xhandler@h /* Vector 0 - NMI */ - .long _cwp_lolimit@h /* Vector 1 - underflow */ +#if defined(CFG_NIOS_CPU_OCI_BASE) + /* OCI does the reset job */ + .long _def_xhandler@h /* Vector 0 - NMI / Reset */ +#else + /* there is no OCI, so we have to do a direct reset jump here */ + .long CFG_NIOS_CPU_RST_VECT /* Vector 0 - Reset to GERMS */ +#endif + .long _cwp_lolimit@h /* Vector 1 - underflow */ .long _cwp_hilimit@h /* Vector 2 - overflow */ .long _def_xhandler@h /* Vector 3 - GNUPro debug */ @@ -72,7 +81,11 @@ _vectors: .long _def_xhandler@h /* Vector 13 - future reserved */ .long _def_xhandler@h /* Vector 14 - future reserved */ .long _def_xhandler@h /* Vector 15 - future reserved */ +#if (CFG_NIOS_TMRIRQ == 16) + .long _timebase_int@h /* Vector 16 - lopri timer*/ +#else .long _def_xhandler@h /* Vector 16 */ +#endif .long _def_xhandler@h /* Vector 17 */ .long _def_xhandler@h /* Vector 18 */ .long _def_xhandler@h /* Vector 19 */ @@ -106,7 +119,11 @@ _vectors: .long _def_xhandler@h /* Vector 47 */ .long _def_xhandler@h /* Vector 48 */ .long _def_xhandler@h /* Vector 49 */ +#if (CFG_NIOS_TMRIRQ == 50) .long _timebase_int@h /* Vector 50 - lopri timer*/ +#else + .long _def_xhandler@h /* Vector 50 */ +#endif .long _def_xhandler@h /* Vector 51 */ .long _def_xhandler@h /* Vector 52 */ .long _def_xhandler@h /* Vector 53 */ diff -purN -x CVS u-boot-20040130cvs-dk1xxx_split_conf/doc/README.dk1s10_mldk20 u-boot-20040130cvs-dk1s10_mtx_ldk_20/doc/README.dk1s10_mldk20 --- u-boot-20040130cvs-dk1xxx_split_conf/doc/README.dk1s10_mldk20 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-20040130cvs-dk1s10_mtx_ldk_20/doc/README.dk1s10_mldk20 2004-02-01 01:06:04.000000000 +0100 @@ -0,0 +1,286 @@ + +TODO: specify IDE i/f + + +=============================================================================== + C P U , M E M O R Y , I N / O U T C O M P O N E N T S +=============================================================================== +see also [1]-[5] + +CPU: "LDK2" + 32 bit NIOS for 75 MHz + 512 Byte for register file (30 levels) + with out instruction cache + with out data cache + 2 KByte On Chip ROM with GERMS boot monitor + with out On Chip RAM + MSTEP multiplier + no Debug Core + no On Chip Instrumentation (OCI) + + U-Boot CFG: CFG_NIOS_CPU_CLK = 75000000 + CFG_NIOS_CPU_ICACHE = (not present) + CFG_NIOS_CPU_DCACHE = (not present) + CFG_NIOS_CPU_REG_NUMS = 512 + CFG_NIOS_CPU_MUL = 0 + CFG_NIOS_CPU_MSTEP = 1 + CFG_NIOS_CPU_DBG_CORE = 0 + +IRQ: Nr. | used by + ------+-------------------------------------------------------- + 16 | TIMER0 | CFG_NIOS_CPU_TIMER0_IRQ = 16 + 17 | UART0 | CFG_NIOS_CPU_UART0_IRQ = 17 + 18 | UART1 | CFG_NIOS_CPU_UART1_IRQ = 18 + 20 | LAN91C111 | CFG_NIOS_CPU_LAN0_IRQ = 20 + 25 | IDE0 | CFG_NIOS_CPU_IDE0_IRQ = 25 + +MEMORY: 8 MByte Flash + 16 MByte SDRAM + +Timer: TIMER0: high priority programmable timer (IRQ16) + + U-Boot CFG: CFG_NIOS_CPU_TICK_TIMER = 0 + CFG_NIOS_CPU_USER_TIMER = (not present) + +PIO: Nr. | description + ------+-------------------------------------------------------- + PIO0 | CFPOWER: 1 output to controll CF power supply + PIO1 | BUTTON: 4 inputs for user push buttons (no IRQ) + ------+-------------------------------------------------------- + not | LCD: 11 in/outputs for ASCII LCD + pres.| LED: 8 outputs for user LEDs + | SEVENSEG: 16 outputs for user seven segment display + | RECONF: 1 in/output for . . . . . . . . . . . . + | CFPRESENT: 1 input for CF present event (IRQ35) + | CFATASEL: 1 output to controll CF ATA card select + + U-Boot CFG: CFG_NIOS_CPU_BUTTON_PIO = 1 + CFG_NIOS_CPU_LCD_PIO = (not present) + CFG_NIOS_CPU_LED_PIO = (not present) + CFG_NIOS_CPU_SEVENSEG_PIO = (not present) + CFG_NIOS_CPU_RECONF_PIO = (not present) + CFG_NIOS_CPU_CFPRESENT_PIO = (not present) + CFG_NIOS_CPU_CFPOWER_PIO = 0 + CFG_NIOS_CPU_CFATASEL_PIO = (not present) + +UART: UART0: fixed baudrate of 115200, fixed protocol 8N2, + without handshake RTS/CTS (IRQ17) + UART1: fixed baudrate of 115200, fixed protocol 8N1, + without handshake RTS/CTS (IRQ18) + +LAN: SMsC LAN91C111 with: + - offset 0x300 (LAN91C111_REGISTERS_OFFSET) + - data bus width 32 bit (LAN91C111_DATA_BUS_WIDTH) + +IDE: (TODO) + + +=============================================================================== + M E M O R Y M A P +=============================================================================== + +- - - - - - - - - - - external memory - - - - - - - - - - - - - - - - - - - + + 0x02000000 ---32-----------16|15------------0- CFG_NIOS_CPU_STACK + 0x02000000 --+32-----------16|15------------0+ + | . | \ \ + | . | | | + | . | | > stack area + | . | | | + | . | | V + | . | | + | . | | + SDRAM | . | > CFG_NIOS_CPU_SDRAM_SIZE + | . | | = 0x01000000 + | . | | + 0x01000100 |- - - - - - - - - - - - - - - -+-|- + | . | | \ + | . | | | + | . | | > CFG_NIOS_CPU_VEC_SIZE + | . | | | = 0x00000100 + | | / / + 0x01000000 |- - - - - - - - - - - - - - - -+- - CFG_NIOS_CPU_VEC_BASE + 0x01000000 ---32-----------16|15------------0- CFG_NIOS_CPU_SDRAM_BASE + | sector 127 | \ + + 0x7f0000 |- - - - - - - - - - - - - - - -| | + | : | | + Flash |- - - - : - - - -| > CFG_NIOS_CPU_FLASH_SIZE + | sector 1 : | | = 0x00800000 + + 0x010000 |- - - - - - - - - - - - - - - -| | + | sector 0 (size = 0x10000) | / + 0x00800000 ---8-------------4|3-------------0- CFG_NIOS_CPU_FLASH_BASE + | | + : gap : + : : + +- - - - - - - - - - - external i/o - - - - - - - - - - - - - - - - - - - + + : : + : gap : + | | + 0x00020000 ---32-----------16|15------------0- + | gap | \ + 0x00010310 --+-------------------------------| | + | | | + | register bank (size = 0x10) | | + | +--------.---.---.--- | | + | | bank 0 \ 1 \ 2 \ 3 \ | | + | |---------------------------+ | | + LAN91C111 | | BANK | RESERVED | | | + | |- - - - - - -|- - - - - - -| | > na_enet_size + | | RPCR | MIR | | | = 0x00010000 + | |- - - - - - -|- - - - - - -| | | + | | COUNTER | RCR | | | + | |- - - - - - -|- - - - - - -| | | + | | EPH STATUS | TCR | | | + | +---------------------------+ | | + 0x00010300 --+--LAN91C111_REGISTERS_OFFSET---| | + | gap | / + 0x00010000 ---32-----------16|15------------0- CFG_NIOS_CPU_LAN0_BASE + | | + : gap : + : : + +- - - - - - - - - - - on chip i/o - - - - - - - - - - - - - - - - - - - + + : : + : gap : + | | + 0x00000980 ---32-----------16|15------------0- + | | | \ + : (real size : : | + IDE i/f : and content : : > 0x00000080 + [5] : unknown) : : | + | | | / + 0x00000900 ---32-----------16|15------------0- CFG_NIOS_CPU_IDE0 + | | \ + : gap : > (space for PIO4..7) + | | / + 0x000008c0 ---32-----------16|15------------0- + | (unused) | \ + + 0x1c |- - - - - - - - - - - - - - - -| | + | (unused) | | + + 0x18 |- - - - - - - - - - - - - - - -| | + | (unused) | | + + 0x14 |- - - - - - - - - - - - - - - -| | + UART1 | (unused) | > 0x00000020 + [2] + 0x10 |- - - - - - - - - - - - - - - -| | + | control (10 bit) (rw) | | + + 0x0c |- - - - - - - - - - - - - - - -| | + | status (10 bit) (rw) | | + + 0x08 |- - - - - - - - - - - - - - - -| | + | txdata (8 bit) (wo) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | rxdata (8 bit) (ro) | / + 0x000008a0 ---32-----------16|15------------0- CFG_NIOS_CPU_UART1 + | | \ + : gap : > (space for PIO2..3) + | | / + 0x00000880 ---32-----------16|15------------0- + | edgecapture (4 bit) (rw) | \ + + 0x0c |- - - - - - - - - - - - - - - -| | + PIO1 | interruptmask (4 bit) (rw) | | + [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010 + | (unused) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | data (4 bit) (ro) | / + 0x00000870 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO1 + | (unused) | \ + + 0x0c |- - - - - - - - - - - - - - - -| | + PIO0 | (unused) | | + [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010 + | (unused) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | data (1 bit) (wo) | / + 0x00000860 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO0 + | (unused) | \ + + 0x1c |- - - - - - - - - - - - - - - -| | + | (unused) | | + + 0x18 |- - - - - - - - - - - - - - - -| | + | snaph (16 bit) (rw) | | + + 0x14 |- - - - - - - - - - - - - - - -| | + TIMER0 | snapl (16 bit) (rw) | | + [3] + 0x10 |- - - - - - - - - - - - - - - -| > 0x00000020 + | periodh (16 bit) (rw) | | + + 0x0c |- - - - - - - - - - - - - - - -| | + | periodl (16 bit) (rw) | | + + 0x08 |- - - - - - - - - - - - - - - -| | + | control (4 bit) (rw) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | status (2 bit) (rw) | / + 0x00000840 ---32-----------16|15------------0- CFG_NIOS_CPU_TIMER0 + | | \ + : gap : > (space for UART2) + | | / + 0x00000820 ---32-----------16|15------------0- + | (unused) | \ + + 0x1c |- - - - - - - - - - - - - - - -| | + | (unused) | | + + 0x18 |- - - - - - - - - - - - - - - -| | + | (unused) | | + + 0x14 |- - - - - - - - - - - - - - - -| | + UART0 | (unused) | > 0x00000020 + [2] + 0x10 |- - - - - - - - - - - - - - - -| | + | control (10 bit) (rw) | | + + 0x0c |- - - - - - - - - - - - - - - -| | + | status (10 bit) (rw) | | + + 0x08 |- - - - - - - - - - - - - - - -| | + | txdata (8 bit) (wo) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | rxdata (8 bit) (ro) | / + 0x00000800 ---32-----------16|15------------0- CFG_NIOS_CPU_UART0 + +- - - - - - - - - - - on chip memory 1 - - - - - - - - - - - + + 0x00000800 ---32-----------16|15------------0- + | : | \ + | : | | + GERMS | : | > CFG_NIOS_CPU_ROM_SIZE + | : | | = 0x00000800 + | : | / + 0x00000000 |- - - - - - - - - - - - - - - -+- - CFG_NIOS_CPU_RST_VECT + 0x00000000 ---32-----------16|15------------0- CFG_NIOS_CPU_ROM_BASE + +=============================================================================== + F L A S H M E M O R Y A L L O C A T I O N +=============================================================================== + + 0x01000000 ---8-------------4|3-------------0- + | : | \ + SAFE | : | > 1 MByte + FPGA conf. | : | / (NOT usable by software) + 0x00f00000 --+- - - - - - - -:- - - - - - - -+- + | : | \ + USER | : | > 1 MByte + FPGA conf. | : | / (NOT usable by software) + 0x00e00000 --+- - - - - - - -:- - - - - - - -+- + | : | \ + | : | | + WEB pages | : | > 2 MByte + | : | | (provisory usable) + | : | / + 0x00c00000 --+- - - - - - - -:- - - - - - - -+- + | : | \ + | : | | + | : | | + | : | > 4 MByte free for use + | : | | + 0x00840000 --+- - - - - - - -:- - - - - - - -+-|- u-boot environment + | : | / + 0x00800000 |- - - - - - - -:- - - - - - - -+- - u-boot _start() + 0x00800000 ---8-------------4|3-------------0- + + +=============================================================================== + R E F E R E N C E S +=============================================================================== +[1] http://www.altera.com/literature/manual/mnl_nios_board_stratix_1s10.pdf +[2] http://www.altera.com/literature/ds/ds_nios_uart.pdf +[3] http://www.altera.com/literature/ds/ds_nios_timer.pdf +[4] http://www.altera.com/literature/ds/ds_nios_pio.pdf +[5] http://www.opencores.org/projects/ata/ + http://www.t13.org/index.html + + +=============================================================================== +Stephan Linz diff -purN -x CVS u-boot-20040130cvs-dk1xxx_split_conf/include/configs/DK1S10.h u-boot-20040130cvs-dk1s10_mtx_ldk_20/include/configs/DK1S10.h --- u-boot-20040130cvs-dk1xxx_split_conf/include/configs/DK1S10.h 2004-02-01 00:59:06.000000000 +0100 +++ u-boot-20040130cvs-dk1s10_mtx_ldk_20/include/configs/DK1S10.h 2004-02-01 01:06:04.000000000 +0100 @@ -35,6 +35,8 @@ #include #elif defined(CONFIG_NIOS_STANDARD_32) #include +#elif defined(CONFIG_NIOS_MTX_LDK_20) +#include #else #error *** CFG_ERROR: you have to setup right NIOS CPU configuration #endif @@ -61,8 +63,18 @@ #error *** CFG_ERROR: you have to setup any SDRAM in NIOS CPU config #endif -#define CFG_SRAM_BASE CFG_NIOS_CPU_SRAM_BASE -#define CFG_SRAM_SIZE CFG_NIOS_CPU_SRAM_SIZE +#if defined(CFG_NIOS_CPU_SRAM_BASE) && defined(CFG_NIOS_CPU_SRAM_SIZE) + +#define CFG_SRAM_BASE CFG_NIOS_CPU_SRAM_BASE +#define CFG_SRAM_SIZE CFG_NIOS_CPU_SRAM_SIZE + +#else + +#undef CFG_SRAM_BASE +#undef CFG_SRAM_SIZE + +#endif + #define CFG_VECT_BASE CFG_NIOS_CPU_VEC_BASE /*------------------------------------------------------------------------ @@ -108,7 +120,15 @@ #if (CFG_NIOS_CPU_FLASH_SIZE != 0) #define CFG_ENV_IS_IN_FLASH 1 /* Environment in flash */ + +#if defined(CONFIG_NIOS_STANDARD_32) #define CFG_ENV_ADDR CFG_FLASH_BASE /* Mem addr of env */ +#elif defined(CONFIG_NIOS_MTX_LDK_20) +#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN) +#else +#error *** CFG_ERROR: you have to setup the environment base address CFG_ENV_ADDR +#endif + #define CFG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */ #define CONFIG_ENV_OVERWRITE /* Serial/eth change Ok */ @@ -141,11 +161,18 @@ * TIMER FOR TIMEBASE -- Nios doesn't have the equivalent of ppc PIT, * so an avalon bus timer is required. *----------------------------------------------------------------------*/ -#if (CFG_NIOS_CPU_TIMER_NUMS != 0) +#if (CFG_NIOS_CPU_TIMER_NUMS != 0) && defined(CFG_NIOS_CPU_TICK_TIMER) #if (CFG_NIOS_CPU_TICK_TIMER == 0) -#error *** CFG_ERROR: tick timer at TIMER0 not supported, expand your config.h +#define CFG_NIOS_TMRBASE CFG_NIOS_CPU_TIMER0 /* TIMER0 as tick */ +#define CFG_NIOS_TMRIRQ CFG_NIOS_CPU_TIMER0_IRQ + +#if (CFG_NIOS_CPU_TIMER0_PER >= CFG_HZ) +#define CFG_NIOS_TMRMS (CFG_NIOS_CPU_TIMER0_PER / CFG_HZ) +#else +#error *** CFG_ERROR: you have to use a timer periode of more than CFG_HZ +#endif #elif (CFG_NIOS_CPU_TICK_TIMER == 1) @@ -213,7 +240,7 @@ /*------------------------------------------------------------------------ * STATUS LEDs *----------------------------------------------------------------------*/ -#if (CFG_NIOS_CPU_PIO_NUMS != 0) +#if (CFG_NIOS_CPU_PIO_NUMS != 0) && defined(CFG_NIOS_CPU_LED_PIO) #if (CFG_NIOS_CPU_LED_PIO == 0) @@ -303,7 +330,7 @@ /*------------------------------------------------------------------------ * SEVEN SEGMENT LED DISPLAY *----------------------------------------------------------------------*/ -#if (CFG_NIOS_CPU_PIO_NUMS != 0) +#if (CFG_NIOS_CPU_PIO_NUMS != 0) && defined(CFG_NIOS_CPU_SEVENSEG_PIO) #if (CFG_NIOS_CPU_SEVENSEG_PIO == 0) @@ -442,17 +469,40 @@ #define CFG_MAXARGS 16 /* max number of command args*/ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +/* Default load address */ #if (CFG_SRAM_SIZE != 0) -#define CFG_LOAD_ADDR CFG_SRAM_BASE /* Default load address */ + +/* default in SRAM */ +#define CFG_LOAD_ADDR CFG_SRAM_BASE + +#elif (CFG_SDRAM_SIZE != 0) + +/* default in SDRAM */ +#if (CFG_SDRAM_BASE == CFG_NIOS_CPU_VEC_BASE) +#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + CFG_NIOS_CPU_VEC_SIZE) #else -#undef CFG_LOAD_ADDR +#define CFG_LOAD_ADDR CFG_SDRAM_BASE #endif +#else +#undef CFG_LOAD_ADDR /* force error break */ +#endif + + +/* MEM test area */ #if (CFG_SDRAM_SIZE != 0) -#define CFG_MEMTEST_START CFG_SDRAM_BASE /* SDRAM til stack area */ -#define CFG_MEMTEST_END (CFG_INIT_SP - (1024 * 1024)) /* 1MB stack */ + +/* SDRAM begin to stack area (1MB stack) */ +#if (CFG_SDRAM_BASE == CFG_NIOS_CPU_VEC_BASE) +#define CFG_MEMTEST_START (CFG_SDRAM_BASE + CFG_NIOS_CPU_VEC_SIZE) +#define CFG_MEMTEST_END (CFG_INIT_SP - (1024 * 1024)) +#else +#define CFG_MEMTEST_START CFG_SDRAM_BASE +#define CFG_MEMTEST_END (CFG_INIT_SP - (1024 * 1024)) +#endif + #else -#undef CFG_MEMTEST_START +#undef CFG_MEMTEST_START /* force error break */ #undef CFG_MEMTEST_END #endif diff -purN -x CVS u-boot-20040130cvs-dk1xxx_split_conf/include/configs/DK1S10_mtx_ldk_20.h u-boot-20040130cvs-dk1s10_mtx_ldk_20/include/configs/DK1S10_mtx_ldk_20.h --- u-boot-20040130cvs-dk1xxx_split_conf/include/configs/DK1S10_mtx_ldk_20.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-20040130cvs-dk1s10_mtx_ldk_20/include/configs/DK1S10_mtx_ldk_20.h 2004-02-01 01:06:04.000000000 +0100 @@ -0,0 +1,187 @@ +/* + * (C) Copyright 2003, Li-Pro.Net + * Stephan Linz + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_DK1S10_MTX_LDK_20_H +#define __CONFIG_DK1S10_MTX_LDK_20_H + +/* + * NIOS CPU configuration. (PART OF configs/DK1S10.h) + * + * Here we must define CPU dependencies. Any unsupported option have to + * be defined with zero, example CPU without data cache / OCI: + * + * #define CFG_NIOS_CPU_ICACHE 4096 + * #define CFG_NIOS_CPU_DCACHE 0 + * #define CFG_NIOS_CPU_OCI_BASE 0 + * #define CFG_NIOS_CPU_OCI_SIZE 0 + */ + +/* CPU core */ +#define CFG_NIOS_CPU_CLK 75000000 /* NIOS CPU clock */ +#define CFG_NIOS_CPU_ICACHE (0) /* instruction cache */ +#define CFG_NIOS_CPU_DCACHE (0) /* data cache */ +#define CFG_NIOS_CPU_REG_NUMS 512 /* number of register */ +#define CFG_NIOS_CPU_MUL 0 /* 16x16 MUL: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_MSTEP 1 /* 16x16 MSTEP: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_STACK 0x02000000 /* stack top addr */ +#define CFG_NIOS_CPU_VEC_BASE 0x01000000 /* IRQ vectors addr */ +#define CFG_NIOS_CPU_VEC_SIZE 256 /* size */ +#define CFG_NIOS_CPU_VEC_NUMS 64 /* numbers */ +#define CFG_NIOS_CPU_RST_VECT 0x00000000 /* RESET vector addr */ +#define CFG_NIOS_CPU_DBG_CORE 0 /* CPU debug: no(0) */ + /* yes(1) */ + +/* The offset address in flash to check for the Nios signature "Ni". + * (see GM_FlashExec in germs_monitor.s) */ +#define CFG_NIOS_CPU_EXES_OFFS 0x0C + +/* on-chip extensions */ +#undef CFG_NIOS_CPU_RAM_BASE /* on chip RAM addr */ +#undef CFG_NIOS_CPU_RAM_SIZE /* 64 KB size */ + +#define CFG_NIOS_CPU_ROM_BASE 0x00000000 /* on chip ROM addr */ +#define CFG_NIOS_CPU_ROM_SIZE (2 * 1024) /* 2 KB size */ + +#undef CFG_NIOS_CPU_OCI_BASE /* OCI core addr */ +#undef CFG_NIOS_CPU_OCI_SIZE /* size */ + +/* timer */ +#define CFG_NIOS_CPU_TIMER_NUMS 1 /* number of timer */ + +#define CFG_NIOS_CPU_TIMER0 0x00000840 /* TIMER0 addr */ +#define CFG_NIOS_CPU_TIMER0_IRQ 16 /* IRQ */ +#define CFG_NIOS_CPU_TIMER0_PER 1000 /* periode usec */ +#define CFG_NIOS_CPU_TIMER0_AR 0 /* always run: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_TIMER0_FP 0 /* fixed per: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_TIMER0_SS 1 /* snaphot: no(0) */ + /* yes(1) */ + +/* serial i/o */ +#define CFG_NIOS_CPU_UART_NUMS 2 /* number of uarts */ + +#define CFG_NIOS_CPU_UART0 0x00000800 /* UART0 addr */ +#define CFG_NIOS_CPU_UART0_IRQ 17 /* IRQ */ +#define CFG_NIOS_CPU_UART0_BR 115200 /* baudrate var(0) */ +#define CFG_NIOS_CPU_UART0_DB 8 /* data bit */ +#define CFG_NIOS_CPU_UART0_SB 2 /* stop bit */ +#define CFG_NIOS_CPU_UART0_PA 0 /* parity none(0) */ + /* odd(1) */ + /* even(2) */ +#define CFG_NIOS_CPU_UART0_HS 0 /* handshake: no(0) */ + /* crts(1) */ +#define CFG_NIOS_CPU_UART0_EOP 0 /* eop reg: no(0) */ + /* yes(1) */ + +#define CFG_NIOS_CPU_UART1 0x000008a0 /* UART1 addr */ +#define CFG_NIOS_CPU_UART1_IRQ 18 /* IRQ */ +#define CFG_NIOS_CPU_UART1_BR 115200 /* baudrate var(0) */ +#define CFG_NIOS_CPU_UART1_DB 8 /* data bit */ +#define CFG_NIOS_CPU_UART1_SB 1 /* stop bit */ +#define CFG_NIOS_CPU_UART1_PA 0 /* parity none(0) */ + /* odd(1) */ + /* even(2) */ +#define CFG_NIOS_CPU_UART1_HS 0 /* handshake: no(0) */ + /* crts(1) */ +#define CFG_NIOS_CPU_UART1_EOP 0 /* eop reg: no(0) */ + /* yes(1) */ + +/* parallel i/o */ +#define CFG_NIOS_CPU_PIO_NUMS 2 /* number of parports */ + +#define CFG_NIOS_CPU_PIO0 0x00000860 /* PIO0 addr */ +#undef CFG_NIOS_CPU_PIO0_IRQ /* w/o IRQ */ +#define CFG_NIOS_CPU_PIO0_BITS 1 /* number of bits */ +#define CFG_NIOS_CPU_PIO0_TYPE 1 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO0_CAP 0 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO0_EDGE 0 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO0_ITYPE 0 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +#define CFG_NIOS_CPU_PIO1 0x00000870 /* PIO1 addr */ +#undef CFG_NIOS_CPU_PIO1_IRQ /* w/o IRQ */ +#define CFG_NIOS_CPU_PIO1_BITS 4 /* number of bits */ +#define CFG_NIOS_CPU_PIO1_TYPE 2 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO1_CAP 0 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO1_EDGE 0 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO1_ITYPE 0 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +/* IDE i/f */ +#define CFG_NIOS_CPU_IDE_NUMS 1 /* number of IDE contr. */ +#define CFG_NIOS_CPU_IDE0 0x00000900 /* IDE0 addr */ +#define CFG_NIOS_CPU_IDE0_IRQ 25 /* IRQ */ + +/* memory accessibility */ +#undef CFG_NIOS_CPU_SRAM_BASE /* board SRAM addr */ +#undef CFG_NIOS_CPU_SRAM_SIZE /* 1 MB size */ + +#define CFG_NIOS_CPU_SDRAM_BASE 0x01000000 /* board SDRAM addr */ +#define CFG_NIOS_CPU_SDRAM_SIZE (16*1024*1024) /* 16 MB size */ + +#define CFG_NIOS_CPU_FLASH_BASE 0x00800000 /* board Flash addr */ +#define CFG_NIOS_CPU_FLASH_SIZE (8*1024*1024) /* 8 MB size */ + +/* LAN */ +#define CFG_NIOS_CPU_LAN_NUMS 1 /* number of LAN i/f */ + +#define CFG_NIOS_CPU_LAN0_BASE 0x00010000 /* LAN0 addr */ +#define CFG_NIOS_CPU_LAN0_OFFS 0x0300 /* offset */ +#define CFG_NIOS_CPU_LAN0_IRQ 20 /* IRQ */ +#define CFG_NIOS_CPU_LAN0_BUSW 32 /* buswidth*/ +#define CFG_NIOS_CPU_LAN0_TYPE 0 /* smc91111(0) */ + /* cs8900(1) */ + /* ex: openmac(2) */ + /* ex: alteramac(3) */ + +/* symbolic redefinition (undef, if not present) */ +#define CFG_NIOS_CPU_TICK_TIMER 0 /* TIMER0: tick (needed)*/ +#undef CFG_NIOS_CPU_USER_TIMER /* TIMERx: users choice */ + +#define CFG_NIOS_CPU_CFPOWER_PIO 0 /* PIO0: CF power/sw. */ +#define CFG_NIOS_CPU_BUTTON_PIO 1 /* PIO1: buttons */ +#undef CFG_NIOS_CPU_LCD_PIO /* PIOx: ASCII LCD */ +#undef CFG_NIOS_CPU_LED_PIO /* PIOx: LED bar */ +#undef CFG_NIOS_CPU_SEVENSEG_PIO /* PIOx: 7-seg. display */ +#undef CFG_NIOS_CPU_RECONF_PIO /* PIOx: reconf pin */ +#undef CFG_NIOS_CPU_CFPRESENT_PIO /* PIOx: CF present IRQ */ +#undef CFG_NIOS_CPU_CFATASEL_PIO /* PIOx: CF ATA select */ + +#endif /* __CONFIG_DK1S10_MTX_LDK_20_H */ diff -purN -x CVS u-boot-20040130cvs-dk1xxx_split_conf/lib_nios/board.c u-boot-20040130cvs-dk1s10_mtx_ldk_20/lib_nios/board.c --- u-boot-20040130cvs-dk1xxx_split_conf/lib_nios/board.c 2004-01-21 00:12:34.000000000 +0100 +++ u-boot-20040130cvs-dk1s10_mtx_ldk_20/lib_nios/board.c 2004-02-01 01:06:04.000000000 +0100 @@ -132,8 +132,10 @@ void board_init (void) bd->bi_memstart = CFG_SDRAM_BASE; bd->bi_memsize = CFG_SDRAM_SIZE; bd->bi_flashstart = CFG_FLASH_BASE; +#if defined(CFG_SRAM_BASE) && defined(CFG_SRAM_SIZE) bd->bi_sramstart= CFG_SRAM_BASE; bd->bi_sramsize = CFG_SRAM_SIZE; +#endif bd->bi_baudrate = CONFIG_BAUDRATE; for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) { diff -purN -x CVS u-boot-20040130cvs-dk1xxx_split_conf/MAKEALL u-boot-20040130cvs-dk1s10_mtx_ldk_20/MAKEALL --- u-boot-20040130cvs-dk1xxx_split_conf/MAKEALL 2004-01-04 17:28:35.000000000 +0100 +++ u-boot-20040130cvs-dk1s10_mtx_ldk_20/MAKEALL 2004-02-01 01:06:04.000000000 +0100 @@ -176,7 +176,7 @@ LIST_x86="${LIST_I486}" LIST_nios=" \ DK1C20 DK1C20_standard_32 \ - DK1S10 DK1S10_standard_32 \ + DK1S10 DK1S10_standard_32 DK1S10_mtx_ldk_20 \ " #----------------------------------------------------------------------- diff -purN -x CVS u-boot-20040130cvs-dk1xxx_split_conf/Makefile u-boot-20040130cvs-dk1s10_mtx_ldk_20/Makefile --- u-boot-20040130cvs-dk1xxx_split_conf/Makefile 2004-01-24 21:26:20.000000000 +0100 +++ u-boot-20040130cvs-dk1s10_mtx_ldk_20/Makefile 2004-02-01 01:06:04.000000000 +0100 @@ -1058,6 +1058,7 @@ DK1C20_config: unconfig DK1S10_safe_32_config \ DK1S10_standard_32_config \ +DK1S10_mtx_ldk_20_config \ DK1S10_config: unconfig @ >include/config.h @[ -z "$(findstring _safe_32,$@)" ] || \ @@ -1068,6 +1069,10 @@ DK1S10_config: unconfig { echo "#define CONFIG_NIOS_STANDARD_32 1" >>include/config.h ; \ echo "... NIOS 'standard_32' configuration" ; \ } + @[ -z "$(findstring _mtx_ldk_20,$@)" ] || \ + { echo "#define CONFIG_NIOS_MTX_LDK_20 1" >>include/config.h ; \ + echo "... NIOS 'mtx_ldk_20' configuration" ; \ + } @[ -z "$(findstring DK1S10_config,$@)" ] || \ { echo "#define CONFIG_NIOS_STANDARD_32 1" >>include/config.h ; \ echo "... NIOS 'standard_32' configuration (DEFAULT)" ; \