Dear Semih Hazar,
In message 4BA8FD4E.9080008@indefia.com you wrote:
I'm not the expert on the AVR32 memory architecture, but as far as I know it goes like this for the NOR Flash area: The Flash is mapped at the physical address at 0x0 and this region is cached. This same memory region is also mapped at 0xa000000 which is not cached.
We are aware of this situation, but that was not the actual question.
It's not possible to simply disable caching for 0x0 region. It can be achieved using paging, but it's more complicated.
I have three specific questions:
* Is it technically possible to set up the AVR32 memory controller such that the memory region at 0x0 is mapped uncached?
I am asking if it is possible to configure a system such that cahces are completely turned off.
* Assuming this is possible, then is there a way to reprogram (in the running system) the AVR32 memory controller from one mode (cached) to the other one (uncached) ?
* Does the AVR32 memory controller support anything like a "write-through" cache mode?
If we go with Stefan's option a, then we need to put some #ifdefs or function calls in the flash code to enable/disable cache, right?
Function calls, yes. But ideally we can use write-through, and I expect that we eventually might kept this mode always switched on.
Since caching can't be enabled/disabled in AVR32, the solution Haavard
I still don't buy this statement in this absolute form.
I think all possible scenarios have been talked in the past. I just wanted to submit my patch, since it was way long overdue. If we can't move any further, Wolfgang, I'd like you to accept this patch as it is.
Sorry, but I don't think this is a good solution yet.
Best regards,
Wolfgang Denk