From: Dirk Eibach dirk.eibach@gdsys.cc
For proper displayport performance, scrambling has to be enabled, but is turned off on DP501 by default.
Signed-off-by: Dirk Eibach dirk.eibach@gdsys.cc ---
Changes in v2: None
board/gdsys/common/dp501.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/board/gdsys/common/dp501.c b/board/gdsys/common/dp501.c index 7958bae..7eb15ed 100644 --- a/board/gdsys/common/dp501.c +++ b/board/gdsys/common/dp501.c @@ -61,6 +61,7 @@ void dp501_powerup(u8 addr) i2c_reg_write(addr, 0x71, 0x20); /* Enable Aux burst write */ dp501_setbits(addr, 0x78, 0x30); /* Disable HPD2 IRQ */ dp501_clrbits(addr, 0x2f, 0x40); /* Link FIFO reset selection */ + dp501_clrbits(addr, 0x60, 0x20); /* Enable scrambling */
#ifdef CONFIG_SYS_DP501_VCAPCTRL0 i2c_reg_write(addr, 0x24, CONFIG_SYS_DP501_VCAPCTRL0);