On Jan 21, 2014 5:27 PM, "Stephen Warren" swarren@wwwdotorg.org wrote:
On 10/15/2013 04:54 PM, Tom Warren wrote:
Some T114 peripherals can take up to 8 different clock sources (parents), including 4 new ones that don't exist on previous chips (PLLC2/C3/MEM2/SRC2). Expand clock/pll code/tables to support these additional bits/sources.
Changes were made to some common code. Testing on T30/T20 showed no changes in periph clock sources/divisors.
Also, peripheral clock sources that no longer exist on T114 were removed from the clock_periph_type table (CVE, TVDAC, etc.), and periphs that are gone or not needed in early init are no longer brought out of reset/enabled (FUSE, IRAMA/B/C/D, etc.).
Signed-off-by: Tom Warren twarren@nvidia.com
v2:
- Fixed an assert test for a divisor value (s/b >0, not >=0)
diff --git a/arch/arm/cpu/tegra-common/clock.c
b/arch/arm/cpu/tegra-common/clock.c
@@ -332,7 +343,7 @@ unsigned clock_adjust_periph_pll_div(enum periph_id
periph_id,
if (extra_div) *extra_div = xdiv;
assert(divider >= 0);
assert(divider > 0); if (adjust_periph_pll(periph_id, source, mux_bits, divider)) return -1U; debug("periph %d, rate=%d, reg=%p = %x\n", periph_id, rate,(For context, I'm working on applying the review feedback to this patch myself, so save Tom some time)
I think that's the wrong assert to change.
When I pointed out this issue in V1 of the patch, the problem was inside function clock_periph_enable(). However, that function isn't actually used anywhere, and was dropped from V2 of the patch.
So, unless you tell me otherwise, I think I'll drop the change I quoted above from this patch, since it doesn't seem right.
Sounds good to me.