Fix PCI prefetch region support for PCI bridges
Signed-off-by: Kumar Gala galak@kernel.crashing.org
CHANGELOG: * Fixed PCI prefetch region support for PCI bridges. Since bridges can support separate BARs for Prefetch windows we should set them up if we support a prefetch region
Patch by Kumar Gala 30 Nov 2005
--- commit 9eaf17bb9619be82f24c1ec88829ffe487e67ea8 tree b08f701087b021e21170ff3a74ed034ae4d0c989 parent c087756e1f8aae91b05ae5b5207ba992ef32c238 author Kumar Gala galak@kernel.crashing.org Wed, 30 Nov 2005 12:48:28 -0600 committer Kumar Gala galak@kernel.crashing.org Wed, 30 Nov 2005 12:48:28 -0600
drivers/pci_auto.c | 12 ++++++------ 1 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/pci_auto.c b/drivers/pci_auto.c index b70bacc..15f7432 100644 --- a/drivers/pci_auto.c +++ b/drivers/pci_auto.c @@ -179,10 +179,14 @@ static void pciauto_prescan_setup_bridge pciauto_region_align(pci_prefetch, 0x100000);
/* Set up memory and I/O filter limits, assume 32-bit I/O space */ - pci_hose_write_config_word(hose, dev, PCI_MEMORY_BASE, + pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, (pci_prefetch->bus_lower & 0xfff00000) >> 16);
cmdstat |= PCI_COMMAND_MEMORY; + } else { + /* We don't support prefetchable memory for now, so disable */ + pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000); + pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x1000); }
if (pci_io) { @@ -197,10 +201,6 @@ static void pciauto_prescan_setup_bridge cmdstat |= PCI_COMMAND_IO; }
- /* We don't support prefetchable memory for now, so disable */ - pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000); - pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x1000); - /* Enable memory and I/O accesses, enable bus master */ pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat | PCI_COMMAND_MASTER); } @@ -227,7 +227,7 @@ static void pciauto_postscan_setup_bridg /* Round memory allocator to 1MB boundary */ pciauto_region_align(pci_prefetch, 0x100000);
- pci_hose_write_config_word(hose, dev, PCI_MEMORY_LIMIT, + pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, (pci_prefetch->bus_lower-1) >> 16); }