Hi Miquel,
thank you for review.
On 10/29/2018 11:34 AM, Miquel Raynal wrote:
Hi Vladimir,
Vladimir Zapolskiy vz@mleia.com wrote on Fri, 19 Oct 2018 03:21:18 +0300:
Testing and analysis shows that at the moment LPC32xx NAND SLC driver can not get PL080 DMA backbone support in SPL build, because SPL NAND loaders operate with subpage (ECC step to be precisely) reads, and this is not supported in the NAND SLC + DMA + hardware ECC calculation bundle.
The change removes a cautious build time warning and explicitly disables DMA flavour of the driver for SPL builds, to reduce the amound of #ifdef sections the code blocks are minimally reorganized.
Signed-off-by: Vladimir Zapolskiy vz@mleia.com
Could you please split this patch?
The copyright change should be a patch on its own.
Why? The copyright update is associated with the change. Just a copyright change is meaningless in my humble opinion...
The changes in the coding style without functional changes also.
This is accepted, my position was to lessen the burden on reviewers and maintainers side. If you don't care about it, I'll drop the cleanup change and send v2, but my comprehension that the meaning is pretty low.
Then you can do your changes about removing DMA support for SPL.
However, on this topic, I'm not sure this is a wise idea. Maybe the SPL should be fixed so that it can work with DMA?
Not at the moment. Generally the problem is related to SPL NAND base code, which assumes that subpage reads (ECC block size) are always possible, but that's not the case for this particular NAND controller working in DMA mode.
So, if/when this is fixed in drivers/mtd/nand/raw/nand_spl_simple.c, only then I can consider to remove the guard in my driver.
-- Best wishes, Vladimir