Signed-off-by: Priyanka Jain priyanka.jain@nxp.com Signed-off-by: Suresh Gupta suresh.gupta@nxp.com --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 1 + arch/arm/dts/fsl-ls2080a-rdb.dts | 22 +++++++++++ board/freescale/ls2080ardb/ls2080ardb.c | 23 +++++++++++- configs/ls2088ardb_qspi_defconfig | 41 ++++++++++++++++++++ include/configs/ls2080a_common.h | 13 ++++++ include/configs/ls2080aqds.h | 14 +------ include/configs/ls2080ardb.h | 58 ++++++++++++++++++++++++++++- 7 files changed, 157 insertions(+), 15 deletions(-) create mode 100644 configs/ls2088ardb_qspi_defconfig
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index b24462b..9bff57f 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -160,6 +160,7 @@ endchoice config SYS_LS_PPA_FW_ADDR hex "Address of PPA firmware loading from" depends on FSL_LS_PPA + default 0x20a00000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A default 0x40500000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT default 0x580a00000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A default 0x60500000 if SYS_LS_PPA_FW_IN_XIP diff --git a/arch/arm/dts/fsl-ls2080a-rdb.dts b/arch/arm/dts/fsl-ls2080a-rdb.dts index 1a1813b..96dfafd 100644 --- a/arch/arm/dts/fsl-ls2080a-rdb.dts +++ b/arch/arm/dts/fsl-ls2080a-rdb.dts @@ -15,6 +15,7 @@ compatible = "fsl,ls2080a-rdb", "fsl,ls2080a";
aliases { + spi0 = &qspi; spi1 = &dspi; }; }; @@ -33,3 +34,24 @@ reg = <0>; }; }; + +&qspi { + bus-num = <0>; + status = "okay"; + + qflash0: s25fs512s@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <50000000>; + reg = <0>; + }; + + qflash1: s25fs512s@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <50000000>; + reg = <1>; + }; +}; diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index ea05ec6..ae0f44f 100644 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -57,12 +57,22 @@ unsigned long long get_qixis_addr(void)
int checkboard(void) { +#ifndef CONFIG_FSL_QSPI u8 sw; +#endif char buf[15];
cpu_name(buf); printf("Board: %s-RDB, ", buf);
+/* + * If QSPI is enabled, CPLD needs to be accessed via I2C, + * but LS2080A/LS2088ARDB boards has limitation that it does + * not support CPLD access via I2C + */ +#ifdef CONFIG_FSL_QSPI + printf("boot from QSPI\n"); +#else sw = QIXIS_READ(arch); printf("Board Arch: V%d, ", sw >> 4); printf("Board version: %c, boot from ", (sw & 0xf) + 'A'); @@ -74,11 +84,13 @@ int checkboard(void) printf("vBank: %d\n", sw); else if (sw == 0x9) puts("NAND\n"); + else if (sw == 0xf) + puts("QSPI\n"); else printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata)); - +#endif puts("SERDES1 Reference : "); printf("Clock1 = 156.25MHz "); printf("Clock2 = 156.25MHz"); @@ -199,6 +211,9 @@ int board_init(void)
int board_early_init_f(void) { +#ifdef CONFIG_SYS_I2C_EARLY_INIT + i2c_early_init_f(); +#endif fsl_lsch3_early_init_f(); return 0; } @@ -321,6 +336,11 @@ void update_spd_address(unsigned int ctrl_num, unsigned int slot, unsigned int *addr) { +/* + * Only Board Rev F supports QSPI_BOOT + * so, no need to check for RevC or lower for QSPI_BOOT + */ +#ifndef CONFIG_QSPI_BOOT u8 sw;
sw = QIXIS_READ(arch); @@ -330,4 +350,5 @@ void update_spd_address(unsigned int ctrl_num, else if (ctrl_num == 1 && slot == 1) *addr = SPD_EEPROM_ADDRESS3; } +#endif } diff --git a/configs/ls2088ardb_qspi_defconfig b/configs/ls2088ardb_qspi_defconfig new file mode 100644 index 0000000..eae843a --- /dev/null +++ b/configs/ls2088ardb_qspi_defconfig @@ -0,0 +1,41 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS2080ARDB=y +CONFIG_FSL_LS_PPA=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb" +# CONFIG_SYS_MALLOC_F is not set +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_EXTRA_OPTIONS="LS2080A" +CONFIG_QSPI_BOOT=y +CONFIG_BOOTDELAY=10 +CONFIG_CMD_GREPENV=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_CACHE=y +CONFIG_OF_CONTROL=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +CONFIG_FSL_CAAM=y +CONFIG_DM_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_SYS_NS16550=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_FSL_DSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_STORAGE=y +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 427f623..969dd89 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -19,6 +19,13 @@ /* Link Definitions */ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
+#ifdef CONFIG_FSL_QSPI +#undef CONFIG_CMD_IMLS +#define CONFIG_QIXIS_I2C_ACCESS +#define CONFIG_SYS_I2C_EARLY_INIT +#define CONFIG_DISPLAY_BOARDINFO_LATE +#endif + /* We need architecture specific misc initializations */
/* Link Definitions */ @@ -28,6 +35,12 @@ #else #define CONFIG_SYS_TEXT_BASE 0x30100000 #endif +#else +#define CONFIG_SYS_TEXT_BASE 0x20100000 +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ +#define CONFIG_ENV_SECT_SIZE 0x10000 #endif
#define CONFIG_SUPPORT_RAW_INITRD diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index beacb99..5e23d1a 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -14,12 +14,6 @@ unsigned long get_board_sys_clk(void); unsigned long get_board_ddr_clk(void); #endif
-#ifdef CONFIG_FSL_QSPI -#undef CONFIG_CMD_IMLS -#define CONFIG_QIXIS_I2C_ACCESS -#define CONFIG_SYS_I2C_EARLY_INIT -#define CONFIG_SYS_I2C_IFDR_DIV 0x7e -#endif
#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() @@ -262,13 +256,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
-#if defined(CONFIG_QSPI_BOOT) -#define CONFIG_SYS_TEXT_BASE 0x20010000 -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ -#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ -#define CONFIG_ENV_SECT_SIZE 0x10000 -#else +#ifndef CONFIG_QSPI_BOOT #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000) #define CONFIG_ENV_SECT_SIZE 0x20000 diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index 2155a89..728c143 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -32,7 +32,11 @@ unsigned long get_board_sys_clk(void); #endif
+#ifdef CONFIG_FSL_QSPI +#define CONFIG_SYS_CLK_FREQ 100000000 +#else #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() +#endif #define CONFIG_DDR_CLK_FREQ 133333333 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
@@ -116,7 +120,9 @@ unsigned long get_board_sys_clk(void); CONFIG_SYS_FLASH_BASE + 0x40000000} #endif
+#ifndef CONFIG_FSL_QSPI #define CONFIG_NAND_FSL_IFC +#endif #define CONFIG_SYS_NAND_MAX_ECCPOS 256 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
@@ -154,7 +160,9 @@ unsigned long get_board_sys_clk(void); #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_MTD_NAND_VERIFY_WRITE +#ifndef CONFIG_FSL_QSPI #define CONFIG_CMD_NAND +#endif
#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
@@ -165,12 +173,14 @@ unsigned long get_board_sys_clk(void); #define QIXIS_LBMAP_DFLTBANK 0x00 #define QIXIS_LBMAP_ALTBANK 0x04 #define QIXIS_LBMAP_NAND 0x09 +#define QIXIS_LBMAP_QSPI 0x0f #define QIXIS_RST_CTL_RESET 0x31 #define QIXIS_RST_CTL_RESET_EN 0x30 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 #define QIXIS_RCW_SRC_NAND 0x119 +#define QIXIS_RCW_SRC_QSPI 0x62 #define QIXIS_RST_FORCE_MEM 0x01
#define CONFIG_SYS_CSPR3_EXT (0x0) @@ -241,11 +251,13 @@ unsigned long get_board_sys_clk(void); #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
+#ifndef CONFIG_QSPI_BOOT #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000) #define CONFIG_ENV_SECT_SIZE 0x20000 #define CONFIG_ENV_SIZE 0x2000 #endif +#endif
/* Debug Server firmware */ #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR @@ -256,6 +268,7 @@ unsigned long get_board_sys_clk(void); /* * I2C */ +#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 #define I2C_MUX_PCA_ADDR 0x75 #define I2C_MUX_PCA_ADDR_PRI 0x75 /* Primary Mux*/
@@ -263,11 +276,18 @@ unsigned long get_board_sys_clk(void); #define I2C_MUX_CH_DEFAULT 0x8
/* SPI */ -#ifdef CONFIG_FSL_DSPI +#if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI) #define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_BAR +#ifdef CONFIG_FSL_DSPI #define CONFIG_SPI_FLASH_STMICRO #endif +#ifdef CONFIG_FSL_QSPI +#define CONFIG_SPI_FLASH_SPANSION +#define FSL_QSPI_FLASH_SIZE (1 << 26) /* 64MB */ +#define FSL_QSPI_FLASH_NUM 2 +#endif +#endif
/* * RTC configuration @@ -347,6 +367,29 @@ unsigned long get_board_sys_clk(void); " 0x580800000 \0" \ BOOTENV #else +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:bank_intlv=auto\0" \ + "scriptaddr=0x80800000\0" \ + "kernel_addr_r=0x81000000\0" \ + "pxefile_addr_r=0x81000000\0" \ + "fdt_addr_r=0x88000000\0" \ + "ramdisk_addr_r=0x89000000\0" \ + "loadaddr=0x80100000\0" \ + "kernel_addr=0x100000\0" \ + "ramdisk_addr=0x800000\0" \ + "ramdisk_size=0x2000000\0" \ + "fdt_high=0xa0000000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "kernel_start=0x21100000\0" \ + "kernel_load=0xa0000000\0" \ + "kernel_size=0x2800000\0" \ + "mcmemsize=0x40000000\0" \ + "fdtfile=fsl-ls2080a-rdb.dtb\0" \ + "mcinitcmd=fsl_mc start mc 0x20300000" \ + " 0x20800000 \0" \ + BOOTENV +#else #define CONFIG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "scriptaddr=0x80800000\0" \ @@ -369,6 +412,7 @@ unsigned long get_board_sys_clk(void); " 0x580800000 \0" \ BOOTENV #endif +#endif
#undef CONFIG_BOOTARGS @@ -378,11 +422,19 @@ unsigned long get_board_sys_clk(void); " hugepagesz=2m hugepages=256"
#undef CONFIG_BOOTCOMMAND +#ifdef CONFIG_QSPI_BOOT +/* Try to boot an on-QSPI kernel first, then do normal distro boot */ +#define CONFIG_BOOTCOMMAND "run mcinitcmd && fsl_mc lazyapply dpl 0x20700000" \ + " && cp.b $kernel_start $kernel_load $kernel_size" \ + " && bootm $kernel_load" \ + " || run distro_bootcmd" +#else /* Try to boot an on-NOR kernel first, then do normal distro boot */ #define CONFIG_BOOTCOMMAND "run mcinitcmd && fsl_mc lazyapply dpl 0x580700000" \ " && cp.b $kernel_start $kernel_load $kernel_size" \ " && bootm $kernel_load" \ " || run distro_bootcmd" +#endif
/* MAC/PHY configuration */ #ifdef CONFIG_FSL_MC_ENET @@ -391,7 +443,11 @@ unsigned long get_board_sys_clk(void); #define CONFIG_PHY_CORTINA #define CONFIG_PHYLIB #define CONFIG_SYS_CORTINA_FW_IN_NOR +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_CORTINA_FW_ADDR 0x20900000 +#else #define CONFIG_CORTINA_FW_ADDR 0x581000000 +#endif #define CONFIG_CORTINA_FW_LENGTH 0x40000
#define CORTINA_PHY_ADDR1 0x10