diff --git a/drivers/serial_pl010.c b/drivers/serial_pl010.c
index 417b6ae..dc798a2 100644
--- a/drivers/serial_pl010.c
+++ b/drivers/serial_pl010.c
@@ -29,14 +29,12 @@
 /* Should be fairly simple to make it work with the PL010 as well */
 
 #include <common.h>
+#include <asm/io.h>
 
 #ifdef CFG_PL010_SERIAL
 
 #include "serial_pl011.h"
 
-#define IO_WRITE(addr, val) (*(volatile unsigned int *)(addr) = (val))
-#define IO_READ(addr) (*(volatile unsigned int *)(addr))
-
 /* Integrator AP has two UARTs, we use the first one, at 38400-8-N-1 */
 #define CONSOLE_PORT CONFIG_CONS_INDEX
 #define baudRate CONFIG_BAUDRATE
@@ -56,7 +54,7 @@ int serial_init (void)
 	/*
 	 ** First, disable everything.
 	 */
-	IO_WRITE (port[CONSOLE_PORT] + UART_PL010_CR, 0x0);
+	writel (0x0, port[CONSOLE_PORT] + UART_PL010_CR);
 
 	/*
 	 ** Set baud rate
@@ -64,43 +62,32 @@ int serial_init (void)
 	 */
 	switch (baudRate) {
 	case 9600:
-		divisor = UART_PL010_BAUD_9600;
-		break;
-
 	case 19200:
-		divisor = UART_PL010_BAUD_9600;
-		break;
-
 	case 38400:
-		divisor = UART_PL010_BAUD_38400;
-		break;
-
 	case 57600:
-		divisor = UART_PL010_BAUD_57600;
-		break;
-
 	case 115200:
-		divisor = UART_PL010_BAUD_115200;
+		divisor = UART_PL010_BAUD2DIVISOR(baudRate);
 		break;
 
 	default:
-		divisor = UART_PL010_BAUD_38400;
+		divisor = UART_PL010_BAUD2DIVISOR(38400);
 	}
 
-	IO_WRITE (port[CONSOLE_PORT] + UART_PL010_LCRM,
-		  ((divisor & 0xf00) >> 8));
-	IO_WRITE (port[CONSOLE_PORT] + UART_PL010_LCRL, (divisor & 0xff));
+	writel (((divisor & 0xf00) >> 8), 
+		port[CONSOLE_PORT] + UART_PL010_LCRM);
+	writel ((divisor & 0xff),
+		port[CONSOLE_PORT] + UART_PL010_LCRL);
 
 	/*
 	 ** Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled.
 	 */
-	IO_WRITE (port[CONSOLE_PORT] + UART_PL010_LCRH,
-		  (UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN));
+	writel ((UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN),
+		port[CONSOLE_PORT] + UART_PL010_LCRH);
 
 	/*
 	 ** Finally, enable the UART
 	 */
-	IO_WRITE (port[CONSOLE_PORT] + UART_PL010_CR, (UART_PL010_CR_UARTEN));
+	writel ((UART_PL010_CR_UARTEN), port[CONSOLE_PORT] + UART_PL010_CR);
 
 	return (0);
 }
@@ -137,10 +124,10 @@ void serial_setbrg (void)
 static void pl010_putc (int portnum, char c)
 {
 	/* Wait until there is space in the FIFO */
-	while (IO_READ (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_TXFF);
+	while (readl (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_TXFF);
 
 	/* Send the character */
-	IO_WRITE (port[portnum] + UART_PL01x_DR, c);
+	writel (c, port[portnum] + UART_PL01x_DR);
 }
 
 static int pl010_getc (int portnum)
@@ -148,14 +135,14 @@ static int pl010_getc (int portnum)
 	unsigned int data;
 
 	/* Wait until there is data in the FIFO */
-	while (IO_READ (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_RXFE);
+	while (readl (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_RXFE);
 
-	data = IO_READ (port[portnum] + UART_PL01x_DR);
+	data = readl (port[portnum] + UART_PL01x_DR);
 
 	/* Check for an error flag */
 	if (data & 0xFFFFFF00) {
 		/* Clear the error */
-		IO_WRITE (port[portnum] + UART_PL01x_ECR, 0xFFFFFFFF);
+		writel (0xFFFFFFFF, port[portnum] + UART_PL01x_ECR);
 		return -1;
 	}
 
@@ -164,7 +151,7 @@ static int pl010_getc (int portnum)
 
 static int pl010_tstc (int portnum)
 {
-	return !(IO_READ (port[portnum] + UART_PL01x_FR) &
+	return !(readl (port[portnum] + UART_PL01x_FR) &
 		 UART_PL01x_FR_RXFE);
 }
 
diff --git a/drivers/serial_pl011.h b/drivers/serial_pl011.h
index 5f20fdd..3a3c52f 100644
--- a/drivers/serial_pl011.h
+++ b/drivers/serial_pl011.h
@@ -77,18 +77,8 @@ #define UART_PL010_LCRH_EPS             
 #define UART_PL010_LCRH_PEN             (1 << 1)
 #define UART_PL010_LCRH_BRK             (1 << 0)
 
+#define UART_PL010_BAUD2DIVISOR(baud)	((CFG_UART_PL010_CLOCK+(0x8*(baud)))/(0x10*(baud))-1)
-#define UART_PL010_BAUD_460800            1
-#define UART_PL010_BAUD_230400            3
-#define UART_PL010_BAUD_115200            7
-#define UART_PL010_BAUD_57600             15
-#define UART_PL010_BAUD_38400             23
-#define UART_PL010_BAUD_19200             47
-#define UART_PL010_BAUD_14400             63
-#define UART_PL010_BAUD_9600              95
-#define UART_PL010_BAUD_4800              191
-#define UART_PL010_BAUD_2400              383
-#define UART_PL010_BAUD_1200              767
 /*
  *  PL011 definitions
  *
diff --git a/include/configs/integratorap.h b/include/configs/integratorap.h
index 2f6e399..b7561ed 100644
--- a/include/configs/integratorap.h
+++ b/include/configs/integratorap.h
@@ -65,6 +65,7 @@ #define CONFIG_PL01x_PORTS	{ (void *) (C
 #define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 #define CFG_SERIAL0		0x16000000
 #define CFG_SERIAL1		0x17000000
+#define CFG_UART_PL010_CLOCK	14745600	/* 14.7456MHz */
 
 /*#define CONFIG_COMMANDS	(CFG_CMD_DHCP | CFG_CMD_IMI | CFG_CMD_NET | CFG_CMD_PING | CFG_CMD_BDI | CFG_CMD_PCI) */
 /*#define CONFIG_NET_MULTI */
