This patch configures and initializes the L2 switch on T1040rdb board. The external L2 switch ports may be connected to PHYs only over QSGMII, for T1040rdb.
Signed-off-by: Codrin Ciubotariu codrin.ciubotariu@freescale.com Change-Id: I56ae23192daa882c66d04b64b9a7d32531a13db0 --- board/freescale/t104xrdb/eth.c | 50 ++++++++++++++++++++++++++++++++++++++++++ include/configs/T104xRDB.h | 6 +++++ 2 files changed, 56 insertions(+)
diff --git a/board/freescale/t104xrdb/eth.c b/board/freescale/t104xrdb/eth.c index f5c0ec8..9d7e119 100644 --- a/board/freescale/t104xrdb/eth.c +++ b/board/freescale/t104xrdb/eth.c @@ -6,11 +6,15 @@
#include <common.h> #include <netdev.h> +#include <asm/fsl_serdes.h> #include <asm/immap_85xx.h> #include <fm_eth.h> #include <fsl_mdio.h> #include <malloc.h> #include <asm/fsl_dtsec.h> +#ifdef CONFIG_VSC9953 +#include <vsc9953.h> +#endif
#include "../common/fman.h"
@@ -81,6 +85,52 @@ int board_eth_init(bd_t *bis) DEFAULT_FM_MDIO_NAME)); }
+#ifdef CONFIG_VSC9953 + phy_interface_t phy_int; + struct mii_dev *bus; + + /* SerDes configured for QSGMII */ + if (serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_A) >= 0) { + for (i = 0; i < 4; i++) { + bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); + phy_addr = CONFIG_SYS_FM1_QSGMII11_PHY_ADDR + i; + phy_int = PHY_INTERFACE_MODE_QSGMII; + + vsc9953_port_info_set_mdio(i, bus); + vsc9953_port_info_set_phy_address(i, phy_addr); + vsc9953_port_info_set_phy_int(i, phy_int); + vsc9953_port_enable(i); + } + } + if (serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_B) >= 0) { + for (i = 4; i < 8; i++) { + bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); + phy_addr = CONFIG_SYS_FM1_QSGMII21_PHY_ADDR + i - 4; + phy_int = PHY_INTERFACE_MODE_QSGMII; + + vsc9953_port_info_set_mdio(i, bus); + vsc9953_port_info_set_phy_address(i, phy_addr); + vsc9953_port_info_set_phy_int(i, phy_int); + vsc9953_port_enable(i); + } + } + + /* Connect DTSEC1 to L2 switch if it doesn't have a PHY */ + if (serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1) < 0) + vsc9953_port_enable(8); + + /* Connect DTSEC2 to L2 switch if it doesn't have a PHY */ + if (serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC2) < 0) { + /* Enable L2 On MAC2 using SCFG */ + struct ccsr_scfg *scfg = (struct ccsr_scfg *) + CONFIG_SYS_MPC85xx_SCFG; + + out_be32(&scfg->esgmiiselcr, in_be32(&scfg->esgmiiselcr) | + (0x80000000)); + vsc9953_port_enable(9); + } +#endif + cpu_eth_init(bis); #endif
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 1eb1371..9a748dd 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -707,6 +707,12 @@ #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02
+#ifdef CONFIG_T1040RDB +#define CONFIG_VSC9953_CMD +#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04 +#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08 +#endif + #define CONFIG_MII /* MII PHY management */ #define CONFIG_ETHPRIME "FM1@DTSEC4" #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */