25 Mar
2011
25 Mar
'11
2:55 p.m.
On Mar 6, 2011, at 10:17 PM, Kumar Gala wrote:
From: Poonam Aggrwal poonam.aggrwal@freescale.com
Changed the following DDR timing parameters for 800Mt/s: tRRT BL/2+1 to BL/2 tWWT BL/2+1 to BL/2 tWRT BL/2+1 to BL/2 tRWT BL/2+1 to BL/2 REFINT 6500ns to 7800ns
Signed-off-by: Poonam Aggrwal poonam.aggrwal@freescale.com Signed-off-by: Kumar Gala galak@kernel.crashing.org
board/freescale/p1_p2_rdb/ddr.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-)
applied to 85xx next
- k