From: Roger Quadros rogerq@ti.com
Not all keystone 2 devices use Davinci NAND controller. Move the platform specific NAND configurations into platform specific headers.
Reported-by: Nishanth Menon nm@ti.com Signed-off-by: Roger Quadros rogerq@ti.com Signed-off-by: Mugunthan V N mugunthanvnm@ti.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- - This fixes the asynchronous abort generated in kernel. Without this patch: http://pastebin.ubuntu.com/15683902/ With this patch: http://pastebin.ubuntu.com/15683889/
board/ti/ks2_evm/board.c | 5 +++++ include/configs/k2e_evm.h | 21 ++++++++++++++++++--- include/configs/k2hk_evm.h | 21 ++++++++++++++++++--- include/configs/k2l_evm.h | 21 ++++++++++++++++++--- include/configs/ti_armv7_keystone2.h | 16 ---------------- 5 files changed, 59 insertions(+), 25 deletions(-)
diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c index e16669d..9e8ad93 100644 --- a/board/ti/ks2_evm/board.c +++ b/board/ti/ks2_evm/board.c @@ -20,6 +20,7 @@
DECLARE_GLOBAL_DATA_PTR;
+#if defined(CONFIG_TI_AEMIF) static struct aemif_config aemif_configs[] = { { /* CS0 */ .mode = AEMIF_MODE_NAND, @@ -33,6 +34,7 @@ static struct aemif_config aemif_configs[] = { .width = AEMIF_WIDTH_8, }, }; +#endif
int dram_init(void) { @@ -42,7 +44,10 @@ int dram_init(void)
gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, CONFIG_MAX_RAM_BANK_SIZE); +#if defined(CONFIG_TI_AEMIF) aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs); +#endif + if (ddr3_size) ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size); return 0; diff --git a/include/configs/k2e_evm.h b/include/configs/k2e_evm.h index 07f975b..8c0f20e 100644 --- a/include/configs/k2e_evm.h +++ b/include/configs/k2e_evm.h @@ -27,14 +27,29 @@ "name_uboot=u-boot-spi-k2e-evm.gph\0" \ "name_fs=arago-console-image-k2e-evm.cpio.gz\0"
+/* NAND Configuration */ +#define CONFIG_SYS_NAND_PAGE_2K +#define CONFIG_NAND_DAVINCI +#define CONFIG_KEYSTONE_RBL_NAND +#define CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE CONFIG_ENV_OFFSET +#define CONFIG_SYS_NAND_MASK_CLE 0x4000 +#define CONFIG_SYS_NAND_MASK_ALE 0x2000 +#define CONFIG_SYS_NAND_CS 2 +#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST +#define CONFIG_SYS_NAND_LARGEPAGE +#define CONFIG_CMD_NAND +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS + +/* AEMIF */ +#define CONFIG_TI_AEMIF +#define CONFIG_AEMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE + #include <configs/ti_armv7_keystone2.h>
/* SPL SPI Loader Configuration */ #define CONFIG_SPL_TEXT_BASE 0x0c100000
-/* NAND Configuration */ -#define CONFIG_SYS_NAND_PAGE_2K - /* Network */ #define CONFIG_KSNET_NETCP_V1_5 #define CONFIG_KSNET_CPSW_NUM_PORTS 9 diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h index a268a86..a23e41d 100644 --- a/include/configs/k2hk_evm.h +++ b/include/configs/k2hk_evm.h @@ -27,14 +27,29 @@ "name_uboot=u-boot-spi-k2hk-evm.gph\0" \ "name_fs=arago-console-image-k2hk-evm.cpio.gz\0"
+/* NAND Configuration */ +#define CONFIG_SYS_NAND_PAGE_2K +#define CONFIG_NAND_DAVINCI +#define CONFIG_KEYSTONE_RBL_NAND +#define CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE CONFIG_ENV_OFFSET +#define CONFIG_SYS_NAND_MASK_CLE 0x4000 +#define CONFIG_SYS_NAND_MASK_ALE 0x2000 +#define CONFIG_SYS_NAND_CS 2 +#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST +#define CONFIG_SYS_NAND_LARGEPAGE +#define CONFIG_CMD_NAND +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS + +/* AEMIF */ +#define CONFIG_TI_AEMIF +#define CONFIG_AEMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE + #include <configs/ti_armv7_keystone2.h>
/* SPL SPI Loader Configuration */ #define CONFIG_SPL_TEXT_BASE 0x0c200000
-/* NAND Configuration */ -#define CONFIG_SYS_NAND_PAGE_2K - /* Network */ #define CONFIG_KSNET_NETCP_V1_0 #define CONFIG_KSNET_CPSW_NUM_PORTS 5 diff --git a/include/configs/k2l_evm.h b/include/configs/k2l_evm.h index f366e67..c1100a1 100644 --- a/include/configs/k2l_evm.h +++ b/include/configs/k2l_evm.h @@ -27,14 +27,29 @@ "name_uboot=u-boot-spi-k2l-evm.gph\0" \ "name_fs=arago-console-image-k2l-evm.cpio.gz\0"
+/* NAND Configuration */ +#define CONFIG_SYS_NAND_PAGE_4K +#define CONFIG_NAND_DAVINCI +#define CONFIG_KEYSTONE_RBL_NAND +#define CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE CONFIG_ENV_OFFSET +#define CONFIG_SYS_NAND_MASK_CLE 0x4000 +#define CONFIG_SYS_NAND_MASK_ALE 0x2000 +#define CONFIG_SYS_NAND_CS 2 +#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST +#define CONFIG_SYS_NAND_LARGEPAGE +#define CONFIG_CMD_NAND +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS + +/* AEMIF */ +#define CONFIG_TI_AEMIF +#define CONFIG_AEMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE + #include <configs/ti_armv7_keystone2.h>
/* SPL SPI Loader Configuration */ #define CONFIG_SPL_TEXT_BASE 0x0c100000
-/* NAND Configuration */ -#define CONFIG_SYS_NAND_PAGE_4K - /* Network */ #define CONFIG_KSNET_NETCP_V1_5 #define CONFIG_KSNET_CPSW_NUM_PORTS 5 diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index 41185a1..84e02b8 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -145,10 +145,6 @@ /* SerDes */ #define CONFIG_TI_KEYSTONE_SERDES
-/* AEMIF */ -#define CONFIG_TI_AEMIF -#define CONFIG_AEMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE - /* I2C Configuration */ #define CONFIG_SYS_I2C_DAVINCI #define CONFIG_SYS_DAVINCI_I2C_SPEED 100000 @@ -167,16 +163,7 @@ #define CONFIG_ENV_EEPROM_IS_ON_I2C
/* NAND Configuration */ -#define CONFIG_NAND_DAVINCI -#define CONFIG_KEYSTONE_RBL_NAND -#define CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE CONFIG_ENV_OFFSET -#define CONFIG_SYS_NAND_MASK_CLE 0x4000 -#define CONFIG_SYS_NAND_MASK_ALE 0x2000 -#define CONFIG_SYS_NAND_CS 2 #define CONFIG_SYS_NAND_USE_FLASH_BBT -#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST - -#define CONFIG_SYS_NAND_LARGEPAGE #define CONFIG_SYS_NAND_BASE_LIST { 0x30000000, } #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_MAX_CHIPS 1 @@ -210,9 +197,6 @@ #define CONFIG_CMD_DHCP #define CONFIG_CMD_PING #define CONFIG_CMD_SAVES -#define CONFIG_CMD_NAND -#define CONFIG_CMD_UBI -#define CONFIG_CMD_UBIFS #define CONFIG_CMD_SF #define CONFIG_CMD_EEPROM #define CONFIG_CMD_USB