On Sel, 2017-08-08 at 11:32 +0200, Marek Vasut wrote:
On 08/08/2017 11:12 AM, tien.fong.chee@intel.com wrote:
From: Tien Fong Chee tien.fong.chee@intel.com
Enable cff driver build which is needed as intermediate driver for handling operation of FPGA program between feeding FPGA design from flash into FPGA manager.
Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com
arch/arm/mach-socfpga/Makefile | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach- socfpga/Makefile index 286bfef..23fb322 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -28,6 +28,7 @@ obj-y += clock_manager_arria10.o obj-y += misc_arria10.o obj-y += pinmux_arria10.o obj-y += reset_manager_arria10.o +obj-y += cff.o
Keep the list sorted ...
Okay.
endif ifdef CONFIG_SPL_BUILD