The SCLK_USB3OTG_REF clocks is used as reference clock for USB3 block.
Add simple support to get rate of SCLK_USB3OTG_REF clocks to fix reference clock period configuration.
Signed-off-by: Jonas Karlman jonas@kwiboo.se --- This has been runtime tested on a Rock64 and NanoPi R2S Plus. --- drivers/clk/rockchip/clk_rk3328.c | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c index 87075ec71340..314b903eaa03 100644 --- a/drivers/clk/rockchip/clk_rk3328.c +++ b/drivers/clk/rockchip/clk_rk3328.c @@ -706,6 +706,9 @@ static ulong rk3328_clk_get_rate(struct clk *clk) case PCLK_HDMIPHY: rate = rk3328_hdmiphy_get_clk(priv->cru); break; + case SCLK_USB3OTG_REF: + rate = OSC_HZ; + break; default: return -ENOENT; } @@ -780,6 +783,7 @@ static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate) case PCLK_DDR: case ACLK_GMAC: case PCLK_GMAC: + case SCLK_USB3OTG_REF: case SCLK_USB3OTG_SUSPEND: case USB480M: return 0;