On Mon, Sep 14, 2020 at 10:23:03AM -0400, Sean Anderson wrote:
This adds comments regarding the ordering and purpose of certain instructions as I understand them.
Signed-off-by: Sean Anderson seanga2@gmail.com Reviewed-by: Bin Meng bin.meng@windriver.com Reviewed-by: Rick Chen rick@andestech.com
Changes in v2:
- Clarify comments regarding tp
arch/riscv/cpu/start.S | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index a16af79fbe..cb1347559c 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -43,7 +43,10 @@ _start: csrr a0, CSR_MHARTID #endif
- /* save hart id and dtb pointer */
- /*
* Save hart id and dtb pointer. The thread pointer register is not* modified by C code. It is used by secondary_hart_loop.*/@@ -54,10 +57,18 @@ _start: */ mv gp, zero
- /*
* Set the trap handler. This must happen after initializing gp because* the handler may use it.*/
- /* mask all interrupts */
- /*
* Mask all interrupts. Interrupts are disabled globally (in m/sstatus)* for U-Boot, but we will need to read m/sip to determine if we get an* IPI*/#if CONFIG_IS_ENABLED(SMP) @@ -410,6 +421,10 @@ secondary_hart_relocate: mv gp, a2 #endif
+/*
- Interrupts are disabled globally, but they can still be read from m/sip. The
- wfi function will wake us up if we get an IPI, even if we do not trap.
- */
secondary_hart_loop: wfi
Reviewed-by: Leo Liang ycliang@andestech.com