On Mon, Mar 31, 2008 at 11:20 AM, Stefan Roese sr@denx.de wrote: <snip>
No, I don't think they are correct. These are the defines for 405EP (and 405GP btw) in ppc405.h (I know this file is hell):
#define GPIO_BASE 0xEF600700 #define GPIO0_OR (GPIO_BASE+0x0) #define GPIO0_TCR (GPIO_BASE+0x4) #define GPIO0_OSRH (GPIO_BASE+0x8) #define GPIO0_OSRL (GPIO_BASE+0xC) #define GPIO0_TSRH (GPIO_BASE+0x10) #define GPIO0_TSRL (GPIO_BASE+0x14) #define GPIO0_ODR (GPIO_BASE+0x18) #define GPIO0_IR (GPIO_BASE+0x1C) #define GPIO0_RR1 (GPIO_BASE+0x20) #define GPIO0_RR2 (GPIO_BASE+0x24) #define GPIO0_ISR1H (GPIO_BASE+0x30) #define GPIO0_ISR1L (GPIO_BASE+0x34) #define GPIO0_ISR2H (GPIO_BASE+0x38) #define GPIO0_ISR2L (GPIO_BASE+0x3C)
And as you pointed out above, this is incorrect. High and low is swapped here.
ppc405ep doesn't have GPIO0_RR2, GPIO0_ISR2H and GPIO0_ISR2L, but the rest conforms with the datasheet, doesn't it?.
No. High and low *are* swapped. I just re-checked with users manual rev 1.08. GPIO0_OSRH has offset 0x0C and GPIO0_OSRL has offset 0x08. So this matches the offsets of all other 4xx GPIO registers I have seen so far.
You're right. This was fixed in v 1.06, so this explains why I and ppc405.h was wrong. btw. v1.10 of the Users Manual is out.
I think you got me wrong here. Here is a example. The numbers in brackets are the offsets for the OSR. The datasheet of 405ep says the address of the high register (0x08) is 4 bytes lower than the low register (0x0C) and the high register is responsible for the pins 0-15. So if gpio_config, with the "broken" code tries to set something for gpio pin 0, it will try to access a low register (0x0C), because on the other cpus the low register is responsible for the pins 0-15. But on 405EP the high register is responsible for pins 0-15. So this is wrong.
Right. The 405EP documentation clearly states that the H register is responsible for pins 0-15 while on other 4xx PPC's the H register is responsible for pins 16-31.
I'm not really sure if this is true though since Taihu is using gpio_set_chip_configuration() without known problems. Could you please re-check with AMCC support, if this statement for 405EP is correct? If this pin assignment of the 405EP GPIO block is incompatible with other GPIO cores, like the one on 440EP or 405EX.
I will do. All ppc405 which used the CFG_GPIO0_*{H,L} defines in their config file were using the "wrong" address.
I think we should first be totally sure about the register offsets and pin assignments before thinking about restructuring the code.
Certainly.
Thanks for your help
Best Wishes
Markus