Describe all SPI CS pins that are not part of the SoC. CS0 can only be used as SPI CS, while CS1, CS2 and CS3 defaults as GPIOs.
Signed-off-by: Miquel Raynal miquel.raynal@bootlin.com --- arch/mips/dts/mscc,ocelot.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+)
diff --git a/arch/mips/dts/mscc,ocelot.dtsi b/arch/mips/dts/mscc,ocelot.dtsi index d1b8868194..8b04f76ed4 100644 --- a/arch/mips/dts/mscc,ocelot.dtsi +++ b/arch/mips/dts/mscc,ocelot.dtsi @@ -135,6 +135,26 @@ pins = "GPIO_12", "GPIO_13"; function = "uart2"; }; + + spi_cs1_pin: spi-cs1-pin { + pins = "GPIO_8"; + function = "si"; + }; + + spi_cs2_pin: spi-cs2-pin { + pins = "GPIO_9"; + function = "si"; + }; + + spi_cs3_pin: spi-cs3-pin { + pins = "GPIO_16"; + function = "si"; + }; + + spi_cs4_pin: spi-cs4-pin { + pins = "GPIO_17"; + function = "si"; + }; }; }; };