Hi Laurent,
Laurent Pinchart laurentp@cse-semaphore.com wrote on 08/22/2007 12:28:36 AM:
Hi Bruce,
ordering. UG322 sheds some light on the issue. D0-D7 are indeed MSB-LSB,
making the SelectMAP interface use the big-endian PPC bit ordering convention.
I'm with Matthaias, I've learned to refer to them as MSB/LSB on the list :). Avoids confusion.
to D7-D0 on the FPGA. I'll go scold our hardware engineer :-)
Don't scold him to hard. It's an easy mistake to make especially if you're used to everything being little endian. (I can say this because I am a HW engineer and I've made this mistake!)
With a properly connected bus between the processor and the FPGA, bit reversal is thus not needed when loading a .bit file (fpga loadb) or a non
mirrored
PROM file (fpga load).
For hardware with bit mirroring on the bus, I suggest either using
amirrored
PROM file or mirroring the bit in the data write callback. I thus vote
for
removing bit mirroring in fpga_loadbitstream() and adding an explanation
of
this issue (either in the code or in the documentation) to prevent
hardware
mistakes in future designs.
I agree with all of this with the exception of totally removing the bit mirroring in fpga_loadbitstream(). If this were going in only a single product or it was being done for the first timeI would be all over that, however we know for a fact that there's at least one board out in the wild that relies on that bit mirroring to take place (another un-enlightened HW engineer no doubt ;) ). Flat out removing the code will break that board and I'm not inclined to face the wrath of the maintainer. If we can figure out who depends on that and get them to push the bit mirroring down to the call back function where it rightfully belongs than I agree remove the code. Otherwise I think it needs to conditionally stay.
Bruce