Signed-off-by: Srikanth Reddy Vintha srikanth.reddy@lntinfotech.com --- arch/arm/cpu/armv7/msm7x27a/acpuclock.c | 6 + arch/arm/include/asm/arch-msm7x27a/iomap.h | 1 + arch/arm/include/asm/arch-msm7x27a/irqs.h | 138 ++++++++++++++++++++++++++++ include/configs/msm7x27a_surf.h | 13 +-- 4 files changed, 151 insertions(+), 7 deletions(-) create mode 100644 arch/arm/include/asm/arch-msm7x27a/irqs.h
diff --git a/arch/arm/cpu/armv7/msm7x27a/acpuclock.c b/arch/arm/cpu/armv7/msm7x27a/acpuclock.c index c144233..7af80ef 100644 --- a/arch/arm/cpu/armv7/msm7x27a/acpuclock.c +++ b/arch/arm/cpu/armv7/msm7x27a/acpuclock.c @@ -222,6 +222,12 @@ void acpu_clock_init(void) udelay(1000); } } +void hsusb_clock_init(void) +{ + /* USB local clock control not enabled; use proc comm */ + usb_clock_init(); +} +
#ifdef CONFIG_QC_MMC /* Configure MMC clock */ diff --git a/arch/arm/include/asm/arch-msm7x27a/iomap.h b/arch/arm/include/asm/arch-msm7x27a/iomap.h index 4c9d434..bc875ff 100644 --- a/arch/arm/include/asm/arch-msm7x27a/iomap.h +++ b/arch/arm/include/asm/arch-msm7x27a/iomap.h @@ -48,6 +48,7 @@
#define MSM_SHARED_BASE 0x00100000
+#define MSM_USB_BASE 0xA0800000 #define MSM_SDC1_BASE 0xA0400000 #define MSM_SDC3_BASE 0xA0600000
diff --git a/arch/arm/include/asm/arch-msm7x27a/irqs.h b/arch/arm/include/asm/arch-msm7x27a/irqs.h new file mode 100644 index 0000000..798fd43 --- /dev/null +++ b/arch/arm/include/asm/arch-msm7x27a/irqs.h @@ -0,0 +1,138 @@ +/* + * Copyright (c) 2008, Google Inc. + * All rights reserved. + * + * (C) Copyright 2012 + * Larsen & Toubro Infotech Ltd. <www.lntinfotech.com> + * + * This source code is dual-licensed. You may use it under the terms of the + * GNU General Public License version 2, or under the license below. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Google, Inc. nor the names of its contributors + * may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _PLATFORM_MSM7K_IRQS_H_ +#define _PLATFORM_MSM7K_IRQS_H_ + +#define VIC_REG(off) (MSM_VIC_BASE + (off)) + +#define VIC_INT_SELECT0 VIC_REG(0x0000) /* 1: FIQ, 0: IRQ */ +#define VIC_INT_SELECT1 VIC_REG(0x0004) /* 1: FIQ, 0: IRQ */ +#define VIC_INT_EN0 VIC_REG(0x0010) +#define VIC_INT_EN1 VIC_REG(0x0014) +#define VIC_INT_ENCLEAR0 VIC_REG(0x0020) +#define VIC_INT_ENCLEAR1 VIC_REG(0x0024) +#define VIC_INT_ENSET0 VIC_REG(0x0030) +#define VIC_INT_ENSET1 VIC_REG(0x0034) +#define VIC_INT_TYPE0 VIC_REG(0x0040) /* 1: EDGE, 0: LEVEL */ +#define VIC_INT_TYPE1 VIC_REG(0x0044) /* 1: EDGE, 0: LEVEL */ +#define VIC_INT_POLARITY0 VIC_REG(0x0050) /* 1: NEG, 0: POS */ +#define VIC_INT_POLARITY1 VIC_REG(0x0054) /* 1: NEG, 0: POS */ +#define VIC_NO_PEND_VAL VIC_REG(0x0060) +#define VIC_INT_MASTEREN VIC_REG(0x0064) /* 1: IRQ, 2: FIQ */ +#define VIC_PROTECTION VIC_REG(0x006C) /* 1: ENABLE */ +#define VIC_CONFIG VIC_REG(0x0068) /* 1: USE ARM1136 VIC */ +#define VIC_IRQ_STATUS0 VIC_REG(0x0080) +#define VIC_IRQ_STATUS1 VIC_REG(0x0084) +#define VIC_FIQ_STATUS0 VIC_REG(0x0090) +#define VIC_FIQ_STATUS1 VIC_REG(0x0094) +#define VIC_RAW_STATUS0 VIC_REG(0x00A0) +#define VIC_RAW_STATUS1 VIC_REG(0x00A4) +#define VIC_INT_CLEAR0 VIC_REG(0x00B0) +#define VIC_INT_CLEAR1 VIC_REG(0x00B4) +#define VIC_SOFTINT0 VIC_REG(0x00C0) +#define VIC_SOFTINT1 VIC_REG(0x00C4) +#define VIC_IRQ_VEC_RD VIC_REG(0x00D0) /* pending int # */ +#define VIC_IRQ_VEC_PEND_RD VIC_REG(0x00D4) /* pending vector addr */ +#define VIC_IRQ_VEC_WR VIC_REG(0x00D8) +#define VIC_IRQ_IN_SERVICE VIC_REG(0x00E0) +#define VIC_IRQ_IN_STACK VIC_REG(0x00E4) +#define VIC_TEST_BUS_SEL VIC_REG(0x00E8) + + +#define INT_A9_M2A_0 0 +#define INT_A9_M2A_1 1 +#define INT_A9_M2A_2 2 +#define INT_A9_M2A_3 3 +#define INT_A9_M2A_4 4 +#define INT_A9_M2A_5 5 +#define INT_A9_M2A_6 6 +#define INT_GP_TIMER_EXP 7 +#define INT_DEBUG_TIMER_EXP 8 +#define INT_UART1 9 +#define INT_UART2 10 +#define INT_UART3 11 +#define INT_UART1_RX 12 +#define INT_UART2_RX 13 +#define INT_UART3_RX 14 +#define INT_USB_OTG 15 +#define INT_MDDI_PRI 16 +#define INT_MDDI_EXT 17 +#define INT_MDDI_CLIENT 18 +#define INT_MDP 19 +#define INT_GRAPHICS 20 +#define INT_ADM_AARM 21 +#define INT_ADSP_A11 22 +#define INT_ADSP_A9_A11 23 +#define INT_SDC1_0 24 +#define INT_SDC1_1 25 +#define INT_SDC2_0 26 +#define INT_SDC2_1 27 +#define INT_KEYSENSE 28 +#define INT_TCHSCRN_SSBI 29 +#define INT_TCHSCRN1 30 +#define INT_TCHSCRN2 31 + +#define INT_GPIO_GROUP1 (32 + 0) +#define INT_GPIO_GROUP2 (32 + 1) +#define INT_PWB_I2C (32 + 2) +#define INT_NAND_WR_ER_DONE (32 + 3) +#define INT_NAND_OP_DONE (32 + 4) +#define INT_SOFTRESET (32 + 5) +#define INT_PBUS_ARM11 (32 + 6) +#define INT_AXI_MPU_SMI (32 + 7) +#define INT_AXI_MPU_EBI1 (32 + 8) +#define INT_AD_HSSD (32 + 9) +#define INT_ARM11_PM (32 + 10) +#define INT_ARM11_DMA (32 + 11) +#define INT_TSIF_IRQ (32 + 12) +#define INT_UART1DM_IRQ (32 + 13) +#define INT_UART1DM_RX (32 + 14) +#define INT_USB_HS (32 + 15) +#define INT_SDC3_0 (32 + 16) +#define INT_SDC3_1 (32 + 17) +#define INT_SDC4_0 (32 + 18) +#define INT_SDC4_1 (32 + 19) +#define INT_UART2DM_RX (32 + 20) +#define INT_UART2DM_IRQ (32 + 21) + +#define MSM_IRQ_BIT(irq) (1 << ((irq) & 31)) + +#define NR_IRQS 54 + + +#endif diff --git a/include/configs/msm7x27a_surf.h b/include/configs/msm7x27a_surf.h index a82ba59..78d6252 100644 --- a/include/configs/msm7x27a_surf.h +++ b/include/configs/msm7x27a_surf.h @@ -38,6 +38,11 @@ */ #define CONFIG_SYS_MALLOC_LEN (2 * 1024) /* 2KB */
+/* Enable USB */ +#define CONFIG_MSM_UDC +#define CONFIG_USB_TTY +#define CONFIG_USB_DEVICE + /* * select serial console configuration */ @@ -60,8 +65,7 @@ #undef CONFIG_CMD_NET /* network support */ #undef CONFIG_SYS_MAX_FLASH_SECT #define CONFIG_EXTRA_ENV_SETTINGS \ - "console=ttyS0,115200n8\0" \ - + "usbtty=cdc_acm\0" #define CONFIG_BOOTDELAY -1
/* @@ -98,7 +102,6 @@ /*--------------------------------------------------------------------- * IRQ Settings */ - #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
@@ -106,10 +109,6 @@ * Physical Memory Map */
-#if 0 -#define CONFIG_BOOTDELAY 0 -#define CONFIG_BOOTCOMMAND "mmc part" -#endif #define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM_1 0x00000000