T2081 QDS is a high-performance computing evaluation, development and test platform supporting the T2081 QorIQ Power Architecture processor.
T2081QDS board Overview ----------------------- - T2081 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz - 2MB shared L2 and 512KB L3 CoreNet platform cache (CPC) - CoreNet fabric supporting coherent and noncoherent transactions with prioritization and bandwidth allocation - 32-/64-bit DDR3/DDR3LP SDRAM memory controller with ECC and interleaving - Ethernet interfaces: - Two on-board 10M/100M/1G bps RGMII ports - Two 10Gbps XFI with on-board SFP+ cage - 1Gbps/2.5Gbps SGMII Riser card - 10Gbps XAUI Riser card - Accelerator: - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC - SerDes: - 8 lanes up to 10.3125GHz - Supports SGMII, HiGig, XFI, XAUI and Aurora debug, - IFC: - 512MB NOR Flash, 2GB NAND Flash, PromJet debug port and Qixis FPGA - eSPI: - Three SPI flash (16MB N25Q128A + 16MB EN25S64 + 512KB SST25WF040) - USB: - Two USB2.0 ports with internal PHY (one Type-A + one micro Type mini-AB) - PCIe: - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV) - eSDHC: - Supports various SD/SDHC/SDXC/eMMC devices with adapter cards and voltage translators - I2C: - Four I2C controllers. - UART: - Dual 4-pins UART serial ports
Signed-off-by: Shengzhou Liu Shengzhou.Liu@freescale.com --- board/freescale/{t2080qds => t208xqds}/Makefile | 6 +- board/freescale/{t2080qds => t208xqds}/ddr.c | 0 board/freescale/{t2080qds => t208xqds}/ddr.h | 0 .../eth_t2080qds.c => t208xqds/eth_t208xqds.c} | 167 +++++++++++++++------ board/freescale/{t2080qds => t208xqds}/law.c | 0 board/freescale/{t2080qds => t208xqds}/pci.c | 0 .../freescale/{t2080qds => t208xqds}/t2080_pbi.cfg | 0 .../freescale/{t2080qds => t208xqds}/t2080_rcw.cfg | 0 .../{t2080qds/t2080qds.c => t208xqds/t208xqds.c} | 89 ++++++++++- .../{t2080qds/t2080qds.h => t208xqds/t208xqds.h} | 0 .../t2080qds_qixis.h => t208xqds/t208xqds_qixis.h} | 8 +- board/freescale/{t2080qds => t208xqds}/tlb.c | 0 boards.cfg | 15 +- include/configs/{T2080QDS.h => T208xQDS.h} | 14 +- 14 files changed, 238 insertions(+), 61 deletions(-) rename board/freescale/{t2080qds => t208xqds}/Makefile (53%) rename board/freescale/{t2080qds => t208xqds}/ddr.c (100%) rename board/freescale/{t2080qds => t208xqds}/ddr.h (100%) rename board/freescale/{t2080qds/eth_t2080qds.c => t208xqds/eth_t208xqds.c} (73%) rename board/freescale/{t2080qds => t208xqds}/law.c (100%) rename board/freescale/{t2080qds => t208xqds}/pci.c (100%) rename board/freescale/{t2080qds => t208xqds}/t2080_pbi.cfg (100%) rename board/freescale/{t2080qds => t208xqds}/t2080_rcw.cfg (100%) rename board/freescale/{t2080qds/t2080qds.c => t208xqds/t208xqds.c} (80%) rename board/freescale/{t2080qds/t2080qds.h => t208xqds/t208xqds.h} (100%) rename board/freescale/{t2080qds/t2080qds_qixis.h => t208xqds/t208xqds_qixis.h} (90%) rename board/freescale/{t2080qds => t208xqds}/tlb.c (100%) rename include/configs/{T2080QDS.h => T208xQDS.h} (99%)
diff --git a/board/freescale/t2080qds/Makefile b/board/freescale/t208xqds/Makefile similarity index 53% rename from board/freescale/t2080qds/Makefile rename to board/freescale/t208xqds/Makefile index 0b8747b..947b7f7 100644 --- a/board/freescale/t2080qds/Makefile +++ b/board/freescale/t208xqds/Makefile @@ -4,8 +4,10 @@ # SPDX-License-Identifier: GPL-2.0+ #
-obj-$(CONFIG_T2080QDS) += t2080qds.o -obj-$(CONFIG_T2080QDS) += eth_t2080qds.o +obj-$(CONFIG_T2080QDS) += t208xqds.o +obj-$(CONFIG_T2080QDS) += eth_t208xqds.o +obj-$(CONFIG_T2081QDS) += t208xqds.o +obj-$(CONFIG_T2081QDS) += eth_t208xqds.o obj-$(CONFIG_PCI) += pci.o obj-y += ddr.o obj-y += law.o diff --git a/board/freescale/t2080qds/ddr.c b/board/freescale/t208xqds/ddr.c similarity index 100% rename from board/freescale/t2080qds/ddr.c rename to board/freescale/t208xqds/ddr.c diff --git a/board/freescale/t2080qds/ddr.h b/board/freescale/t208xqds/ddr.h similarity index 100% rename from board/freescale/t2080qds/ddr.h rename to board/freescale/t208xqds/ddr.h diff --git a/board/freescale/t2080qds/eth_t2080qds.c b/board/freescale/t208xqds/eth_t208xqds.c similarity index 73% rename from board/freescale/t2080qds/eth_t2080qds.c rename to board/freescale/t208xqds/eth_t208xqds.c index 3e4ab8f..f3d7262 100644 --- a/board/freescale/t2080qds/eth_t2080qds.c +++ b/board/freescale/t208xqds/eth_t208xqds.c @@ -25,21 +25,30 @@ #include <asm/fsl_serdes.h> #include "../common/qixis.h" #include "../common/fman.h" -#include "t2080qds_qixis.h" +#include "t208xqds_qixis.h"
#define EMI_NONE 0xFFFFFFFF #define EMI1_RGMII1 0 #define EMI1_RGMII2 1 #define EMI1_SLOT1 2 +#if defined(CONFIG_T2080QDS) #define EMI1_SLOT2 6 #define EMI1_SLOT3 3 #define EMI1_SLOT4 4 #define EMI1_SLOT5 5 -#define EMI2 7 +#elif defined(CONFIG_T2081QDS) +#define EMI1_SLOT2 3 +#define EMI1_SLOT3 4 +#define EMI1_SLOT5 5 +#define EMI1_SLOT6 6 +#define EMI1_SLOT7 7 +#endif +#define EMI2 8
static int mdio_mux[NUM_FM_PORTS];
static const char * const mdio_names[] = { +#if defined(CONFIG_T2080QDS) "T2080QDS_MDIO_RGMII1", "T2080QDS_MDIO_RGMII2", "T2080QDS_MDIO_SLOT1", @@ -48,12 +57,27 @@ static const char * const mdio_names[] = { "T2080QDS_MDIO_SLOT5", "T2080QDS_MDIO_SLOT2", "T2080QDS_MDIO_10GC", +#elif defined(CONFIG_T2081QDS) + "T2081QDS_MDIO_RGMII1", + "T2081QDS_MDIO_RGMII2", + "T2081QDS_MDIO_SLOT1", + "T2081QDS_MDIO_SLOT2", + "T2081QDS_MDIO_SLOT3", + "T2081QDS_MDIO_SLOT5", + "T2081QDS_MDIO_SLOT6", + "T2081QDS_MDIO_SLOT7", + "T2081QDS_MDIO_10GC", +#endif };
/* Map SerDes1 8 lanes to default slot, will be initialized dynamically */ +#if defined(CONFIG_T2080QDS) static u8 lane_to_slot[] = {3, 3, 3, 3, 1, 1, 1, 1}; +#elif defined(CONFIG_T2081QDS) +static u8 lane_to_slot[] = {2, 2, 2, 2, 1, 1, 1, 1}; +#endif
-static const char *T2080qds_mdio_name_for_muxval(u8 muxval) +static const char *t208xqds_mdio_name_for_muxval(u8 muxval) { return mdio_names[muxval]; } @@ -61,7 +85,7 @@ static const char *T2080qds_mdio_name_for_muxval(u8 muxval) struct mii_dev *mii_dev_for_muxval(u8 muxval) { struct mii_dev *bus; - const char *name = T2080qds_mdio_name_for_muxval(muxval); + const char *name = t208xqds_mdio_name_for_muxval(muxval);
if (!name) { printf("No bus for muxval %x\n", muxval); @@ -78,15 +102,15 @@ struct mii_dev *mii_dev_for_muxval(u8 muxval) return bus; }
-struct T2080qds_mdio { +struct t208xqds_mdio { u8 muxval; struct mii_dev *realbus; };
-static void T2080qds_mux_mdio(u8 muxval) +static void t208xqds_mux_mdio(u8 muxval) { u8 brdcfg4; - if (muxval < 7) { + if (muxval < 8) { brdcfg4 = QIXIS_READ(brdcfg[4]); brdcfg4 &= ~BRDCFG4_EMISEL_MASK; brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT); @@ -94,54 +118,54 @@ static void T2080qds_mux_mdio(u8 muxval) } }
-static int T2080qds_mdio_read(struct mii_dev *bus, int addr, int devad, +static int t208xqds_mdio_read(struct mii_dev *bus, int addr, int devad, int regnum) { - struct T2080qds_mdio *priv = bus->priv; + struct t208xqds_mdio *priv = bus->priv;
- T2080qds_mux_mdio(priv->muxval); + t208xqds_mux_mdio(priv->muxval);
return priv->realbus->read(priv->realbus, addr, devad, regnum); }
-static int T2080qds_mdio_write(struct mii_dev *bus, int addr, int devad, +static int t208xqds_mdio_write(struct mii_dev *bus, int addr, int devad, int regnum, u16 value) { - struct T2080qds_mdio *priv = bus->priv; + struct t208xqds_mdio *priv = bus->priv;
- T2080qds_mux_mdio(priv->muxval); + t208xqds_mux_mdio(priv->muxval);
return priv->realbus->write(priv->realbus, addr, devad, regnum, value); }
-static int T2080qds_mdio_reset(struct mii_dev *bus) +static int t208xqds_mdio_reset(struct mii_dev *bus) { - struct T2080qds_mdio *priv = bus->priv; + struct t208xqds_mdio *priv = bus->priv;
return priv->realbus->reset(priv->realbus); }
-static int T2080qds_mdio_init(char *realbusname, u8 muxval) +static int t208xqds_mdio_init(char *realbusname, u8 muxval) { - struct T2080qds_mdio *pmdio; + struct t208xqds_mdio *pmdio; struct mii_dev *bus = mdio_alloc();
if (!bus) { - printf("Failed to allocate T2080QDS MDIO bus\n"); + printf("Failed to allocate t208xqds MDIO bus\n"); return -1; }
pmdio = malloc(sizeof(*pmdio)); if (!pmdio) { - printf("Failed to allocate T2080QDS private data\n"); + printf("Failed to allocate t208xqds private data\n"); free(bus); return -1; }
- bus->read = T2080qds_mdio_read; - bus->write = T2080qds_mdio_write; - bus->reset = T2080qds_mdio_reset; - sprintf(bus->name, T2080qds_mdio_name_for_muxval(muxval)); + bus->read = t208xqds_mdio_read; + bus->write = t208xqds_mdio_write; + bus->reset = t208xqds_mdio_reset; + sprintf(bus->name, t208xqds_mdio_name_for_muxval(muxval));
pmdio->realbus = miiphy_get_dev_by_name(realbusname);
@@ -154,7 +178,6 @@ static int T2080qds_mdio_init(char *realbusname, u8 muxval)
pmdio->muxval = muxval; bus->priv = pmdio; - return mdio_register(bus); }
@@ -177,9 +200,15 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, case FM1_DTSEC2: case FM1_DTSEC9: case FM1_DTSEC10: - sprintf(alias, "phy_sgmii_s3_%x", phy); - fdt_set_phy_handle(fdt, compat, addr, alias); - fdt_status_okay_by_alias(fdt, "emi1_slot3"); + if (mdio_mux[port] == EMI1_SLOT2) { + sprintf(alias, "phy_sgmii_s2_%x", phy); + fdt_set_phy_handle(fdt, compat, addr, alias); + fdt_status_okay_by_alias(fdt, "emi1_slot2"); + } else if (mdio_mux[port] == EMI1_SLOT3) { + sprintf(alias, "phy_sgmii_s3_%x", phy); + fdt_set_phy_handle(fdt, compat, addr, alias); + fdt_status_okay_by_alias(fdt, "emi1_slot3"); + } break; case FM1_DTSEC5: case FM1_DTSEC6: @@ -238,6 +267,7 @@ static void initialize_lane_to_slot(void) srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
switch (srds_s1) { +#if defined(CONFIG_T2080QDS) case 0x51: case 0x5f: case 0x65: @@ -264,6 +294,14 @@ static void initialize_lane_to_slot(void) lane_to_slot[6] = 3; lane_to_slot[7] = 3; break; +#elif defined(CONFIG_T2081QDS) + case 0x6b: + lane_to_slot[4] = 1; + lane_to_slot[5] = 3; + lane_to_slot[6] = 3; + lane_to_slot[7] = 3; + break; +#endif default: break; } @@ -305,14 +343,20 @@ int board_eth_init(bd_t *bis) fm_memac_mdio_init(bis, &tgec_mdio_info);
/* Register the muxing front-ends to the MDIO buses */ - T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1); - T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2); - T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); - T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2); - T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); - T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); - T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5); - T2080qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2); + t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1); + t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2); + t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); + t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2); + t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); +#if defined(CONFIG_T2080QDS) + t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); +#endif + t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5); +#if defined(CONFIG_T2081QDS) + t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT6); + t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7); +#endif + t208xqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
/* Set the two on-board RGMII PHY address */ fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); @@ -327,21 +371,21 @@ int board_eth_init(bd_t *bis) case 0x95: case 0xa2: case 0x94: - /* SGMII in Slot3 */ + /* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot2 */ fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); - /* SGMII in Slot2 */ + /* T2080QDS: SGMII in Slot2; T2081QDS: SGMII in Slot1 */ fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); break; case 0x51: case 0x5f: case 0x65: - /* XAUI/HiGig in Slot3 */ + /* T2080QDS: XAUI/HiGig in Slot3; T2081QDS: in Slot2 */ fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); - /* SGMII in Slot2 */ + /* T2080QDS: SGMII in Slot2; T2081QDS: in Slot3 */ fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); break; @@ -365,7 +409,7 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM1_10GEC2, 5); fm_info_set_phy_address(FM1_10GEC3, 6); fm_info_set_phy_address(FM1_10GEC4, 7); - /* SGMII in Slot2 */ + /* T2080QDS: SGMII in Slot2; T2081QDS: in Slot3 */ fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); break; @@ -373,7 +417,7 @@ int board_eth_init(bd_t *bis) case 0x6d: fm_info_set_phy_address(FM1_10GEC1, 4); fm_info_set_phy_address(FM1_10GEC2, 5); - /* SGMII in Slot3 */ + /* T2080QDS: SGMII in Slot3; T2081QDS: in Slot2 */ fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); break; @@ -408,6 +452,7 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); break; +#if defined(CONFIG_T2080QDS) case 0xd9: case 0xd3: case 0xcb: @@ -419,6 +464,27 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); break; +#elif defined(CONFIG_T2081QDS) + case 0xca: + case 0xcb: + /* SGMII in Slot3 */ + fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); + /* SGMII in Slot5 */ + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); + /* SGMII in Slot6 */ + fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); + /* SGMII in Slot7 */ + fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR); + break; +#endif + case 0xf2: + /* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot7 */ + fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); + break; default: break; } @@ -452,8 +518,25 @@ int board_eth_init(bd_t *bis) case 3: mdio_mux[i] = EMI1_SLOT3; fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); + mdio_mux[i])); + break; +#if defined(CONFIG_T2081QDS) + case 5: + mdio_mux[i] = EMI1_SLOT5; + fm_info_set_mdio(i, mii_dev_for_muxval( + mdio_mux[i])); + break; + case 6: + mdio_mux[i] = EMI1_SLOT6; + fm_info_set_mdio(i, mii_dev_for_muxval( + mdio_mux[i])); + break; + case 7: + mdio_mux[i] = EMI1_SLOT7; + fm_info_set_mdio(i, mii_dev_for_muxval( + mdio_mux[i])); break; +#endif } break; case PHY_INTERFACE_MODE_RGMII: diff --git a/board/freescale/t2080qds/law.c b/board/freescale/t208xqds/law.c similarity index 100% rename from board/freescale/t2080qds/law.c rename to board/freescale/t208xqds/law.c diff --git a/board/freescale/t2080qds/pci.c b/board/freescale/t208xqds/pci.c similarity index 100% rename from board/freescale/t2080qds/pci.c rename to board/freescale/t208xqds/pci.c diff --git a/board/freescale/t2080qds/t2080_pbi.cfg b/board/freescale/t208xqds/t2080_pbi.cfg similarity index 100% rename from board/freescale/t2080qds/t2080_pbi.cfg rename to board/freescale/t208xqds/t2080_pbi.cfg diff --git a/board/freescale/t2080qds/t2080_rcw.cfg b/board/freescale/t208xqds/t2080_rcw.cfg similarity index 100% rename from board/freescale/t2080qds/t2080_rcw.cfg rename to board/freescale/t208xqds/t2080_rcw.cfg diff --git a/board/freescale/t2080qds/t2080qds.c b/board/freescale/t208xqds/t208xqds.c similarity index 80% rename from board/freescale/t2080qds/t2080qds.c rename to board/freescale/t208xqds/t208xqds.c index 4fe8ccb..9cfc0bd 100644 --- a/board/freescale/t2080qds/t2080qds.c +++ b/board/freescale/t208xqds/t208xqds.c @@ -20,8 +20,8 @@
#include "../common/qixis.h" #include "../common/vsc3316_3308.h" -#include "t2080qds.h" -#include "t2080qds_qixis.h" +#include "t208xqds.h" +#include "t208xqds_qixis.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -89,19 +89,22 @@ int select_i2c_ch_pca9547(u8 ch) int brd_mux_lane_to_slot(void) { ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - u32 srds_prtcl_s1, srds_prtcl_s2; + u32 srds_prtcl_s1;
srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL; srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; - srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) & +#if defined(CONFIG_T2080QDS) + u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL; srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; +#endif
switch (srds_prtcl_s1) { case 0: /* SerDes1 is not enabled */ break; +#if defined(CONFIG_T2080QDS) case 0x1c: case 0xa2: /* SD1(A:D) => SLOT3 SGMII @@ -180,12 +183,89 @@ int brd_mux_lane_to_slot(void) */ QIXIS_WRITE(brdcfg[12], 0x1a); break; +#elif defined(CONFIG_T2081QDS) + case 0x51: + /* SD1(A:D) => SLOT2 XAUI + * SD1(E) => SLOT1 PCIe4 x1 + * SD1(F:H) => SLOT3 SGMII + */ + QIXIS_WRITE(brdcfg[12], 0x98); + QIXIS_WRITE(brdcfg[13], 0x70); + break; + case 0x6b: + /* SD1(A:D) => XFI SFP Module + * SD1(E) => SLOT1 PCIe4 x1 + * SD1(F:H) => SLOT3 SGMII + */ + QIXIS_WRITE(brdcfg[12], 0x80); + QIXIS_WRITE(brdcfg[13], 0x70); + break; + case 0x6c: + /* SD1(A:B) => XFI SFP Module + * SD1(C:D) => SLOT2 SGMII + * SD1(E:H) => SLOT1 PCIe4 x4 + */ + QIXIS_WRITE(brdcfg[12], 0xe8); + QIXIS_WRITE(brdcfg[13], 0x0); + break; + case 0x6d: + /* SD1(A:B) => XFI SFP Module + * SD1(C:D) => SLOT2 SGMII + * SD1(E:H) => SLOT1 PCIe4 x4 + */ + QIXIS_WRITE(brdcfg[12], 0xe8); + QIXIS_WRITE(brdcfg[13], 0x0); + break; + case 0xaa: + case 0xab: + /* SD1(A:D) => SLOT2 PCIe3 x4 + * SD1(F:H) => SLOT1 SGMI4 x4 + */ + QIXIS_WRITE(brdcfg[12], 0xf8); + QIXIS_WRITE(brdcfg[13], 0x0); + break; + case 0xca: + case 0xcb: + /* SD1(A) => SLOT2 PCIe3 x1 + * SD1(B) => SLOT7 SGMII + * SD1(C) => SLOT6 SGMII + * SD1(D) => SLOT5 SGMII + * SD1(E) => SLOT1 PCIe4 x1 + * SD1(F:H) => SLOT3 SGMII + */ + QIXIS_WRITE(brdcfg[12], 0x80); + QIXIS_WRITE(brdcfg[13], 0x70); + break; + case 0xde: + case 0xdf: + /* SD1(A:D) => SLOT2 PCIe3 x4 + * SD1(E) => SLOT1 PCIe4 x1 + * SD1(F) => SLOT4 PCIe1 x1 + * SD1(G) => SLOT3 PCIe2 x1 + * SD1(H) => SLOT7 SGMII + */ + QIXIS_WRITE(brdcfg[12], 0x98); + QIXIS_WRITE(brdcfg[13], 0x25); + break; + case 0xf2: + /* SD1(A) => SLOT2 PCIe3 x1 + * SD1(B:D) => SLOT7 SGMII + * SD1(E) => SLOT1 PCIe4 x1 + * SD1(F) => SLOT4 PCIe1 x1 + * SD1(G) => SLOT3 PCIe2 x1 + * SD1(H) => SLOT7 SGMII + */ + QIXIS_WRITE(brdcfg[12], 0x81); + QIXIS_WRITE(brdcfg[13], 0xa5); + break; +#endif default: printf("WARNING: unsupported for SerDes1 Protocol %d\n", srds_prtcl_s1); return -1; }
+#ifdef CONFIG_T2080QDS switch (srds_prtcl_s2) { case 0: /* SerDes2 is not enabled */ @@ -241,6 +321,7 @@ int brd_mux_lane_to_slot(void) srds_prtcl_s2); return -1; } +#endif return 0; }
diff --git a/board/freescale/t2080qds/t2080qds.h b/board/freescale/t208xqds/t208xqds.h similarity index 100% rename from board/freescale/t2080qds/t2080qds.h rename to board/freescale/t208xqds/t208xqds.h diff --git a/board/freescale/t2080qds/t2080qds_qixis.h b/board/freescale/t208xqds/t208xqds_qixis.h similarity index 90% rename from board/freescale/t2080qds/t2080qds_qixis.h rename to board/freescale/t208xqds/t208xqds_qixis.h index fc83da7..bdcdc12 100644 --- a/board/freescale/t2080qds/t2080qds_qixis.h +++ b/board/freescale/t208xqds/t208xqds_qixis.h @@ -4,10 +4,10 @@ * SPDX-License-Identifier: GPL-2.0+ */
-#ifndef __T2080QDS_QIXIS_H__ -#define __T2080QDS_QIXIS_H__ +#ifndef __T208xQDS_QIXIS_H__ +#define __T208xQDS_QIXIS_H__
-/* Definitions of QIXIS Registers for T2080QDS */ +/* Definitions of QIXIS Registers for T208xQDS */
#define QIXIS_SRDS1CLK_122 0x5a #define QIXIS_SRDS1CLK_125 0x5e @@ -35,6 +35,8 @@
#define BRDCFG5_IRE 0x20 /* i2c Remote i2c1 enable */
+#define BRDCFG9_SFP_TX_EN 0x10 + #define BRDCFG12_SD3EN_MASK 0x20 #define BRDCFG12_SD3MX_MASK 0x08 #define BRDCFG12_SD3MX_SLOT5 0x08 diff --git a/board/freescale/t2080qds/tlb.c b/board/freescale/t208xqds/tlb.c similarity index 100% rename from board/freescale/t2080qds/tlb.c rename to board/freescale/t208xqds/tlb.c diff --git a/boards.cfg b/boards.cfg index 706ec96..3b24e1d 100644 --- a/boards.cfg +++ b/boards.cfg @@ -972,11 +972,16 @@ Active powerpc mpc85xx - freescale p2041rdb Active powerpc mpc85xx - freescale t1040qds T1040QDS T1040QDS:PPC_T1040 Poonam Aggrwal poonam.aggrwal@freescale.com Active powerpc mpc85xx - freescale t104xrdb T1040RDB T1040RDB:PPC_T1040 Poonam Aggrwal poonam.aggrwal@freescale.com Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI T1042RDB_PI:PPC_T1042 Poonam Aggrwal poonam.aggrwal@freescale.com -Active powerpc mpc85xx - freescale t2080qds T2080QDS T2080QDS:PPC_T2080 - -Active powerpc mpc85xx - freescale t2080qds T2080QDS_NAND T2080QDS:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 - -Active powerpc mpc85xx - freescale t2080qds T2080QDS_SDCARD T2080QDS:PPC_T2080,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 - -Active powerpc mpc85xx - freescale t2080qds T2080QDS_SPIFLASH T2080QDS:PPC_T2080,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - -Active powerpc mpc85xx - freescale t2080qds T2080QDS_SRIO_PCIE_BOOT T2080QDS:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale t208xqds T2080QDS T208xQDS:PPC_T2080 +Active powerpc mpc85xx - freescale t208xqds T2080QDS_SDCARD T208xQDS:PPC_T2080, RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 +Active powerpc mpc85xx - freescale t208xqds T2080QDS_SPIFLASH T208xQDS:PPC_T2080, RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 +Active powerpc mpc85xx - freescale t208xqds T2080QDS_NAND T208xQDS:PPC_T2080, RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 +Active powerpc mpc85xx - freescale t208xqds T2080QDS_SRIO_PCIE_BOOT T208xQDS:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 +Active powerpc mpc85xx - freescale t208xqds T2081QDS T208xQDS:PPC_T2081 +Active powerpc mpc85xx - freescale t208xqds T2081QDS_SDCARD T208xQDS:PPC_T2081, RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 +Active powerpc mpc85xx - freescale t208xqds T2081QDS_SPIFLASH T208xQDS:PPC_T2081, RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 +Active powerpc mpc85xx - freescale t208xqds T2081QDS_NAND T208xQDS:PPC_T2081, RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 +Active powerpc mpc85xx - freescale t208xqds T2081QDS_SRIO_PCIE_BOOT T208xQDS:PPC_T2081, SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 Active powerpc mpc85xx - freescale t4qds T4160QDS T4240QDS:PPC_T4160 - Active powerpc mpc85xx - freescale t4qds T4160QDS_SDCARD T4240QDS:PPC_T4160,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale t4qds T4160QDS_SPIFLASH T4240QDS:PPC_T4160,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - diff --git a/include/configs/T2080QDS.h b/include/configs/T208xQDS.h similarity index 99% rename from include/configs/T2080QDS.h rename to include/configs/T208xQDS.h index 9bd0fe2..aab9411 100644 --- a/include/configs/T2080QDS.h +++ b/include/configs/T208xQDS.h @@ -5,21 +5,25 @@ */
/* - * T2080 QDS board configuration file + * T2080/T2081 QDS board configuration file */
-#ifndef __T2080QDS_H -#define __T2080QDS_H +#ifndef __T208xQDS_H +#define __T208xQDS_H
-#define CONFIG_T2080QDS #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ #define CONFIG_MMC #define CONFIG_SPI_FLASH #define CONFIG_USB_EHCI +#if defined(CONFIG_PPC_T2080) +#define CONFIG_T2080QDS #define CONFIG_FSL_SATA_V2 #define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */ #define CONFIG_SRIO1 /* SRIO port 1 */ #define CONFIG_SRIO2 /* SRIO port 2 */ +#elif defined(CONFIG_PPC_T2081) +#define CONFIG_T2081QDS +#endif
/* High Level Configuration Options */ #define CONFIG_PHYS_64BIT @@ -801,4 +805,4 @@ unsigned long get_board_ddr_clk(void); #undef CONFIG_CMD_USB #endif
-#endif /* __T2080QDS_H */ +#endif /* __T208xQDS_H */