From: Yau Wai Gan yau.wai.gan@intel.com
This enable the capability to automatically perform FPGA configuration when booting Linux FIT image via bootm command. The FPGA configuration bitstream shall be packed within the FIT image.
Signed-off-by: Yau Wai Gan yau.wai.gan@intel.com Signed-off-by: Jit Loon Lim jit.loon.lim@intel.com --- drivers/fpga/altera.c | 41 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+)
diff --git a/drivers/fpga/altera.c b/drivers/fpga/altera.c index 10c0475d25..35eb95544d 100644 --- a/drivers/fpga/altera.c +++ b/drivers/fpga/altera.c @@ -10,6 +10,10 @@ /* * Altera FPGA support */ +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || \ + IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10) +#include <asm/arch/misc.h> +#endif #include <common.h> #include <errno.h> #include <ACEX1K.h> @@ -49,6 +53,43 @@ static const struct altera_fpga { #endif };
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || \ + IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10) +int fpga_is_partial_data(int devnum, size_t img_len) +{ + /* + * The FPGA data (full or partial) is checked by + * the SDM hardware, for Intel SDM Mailbox based + * devices. Hence always return full bitstream. + * + * For Cyclone V and Arria 10 family, the bitstream + * type paramater is not handled by the driver. + */ + return 0; +} + +int fpga_loadbitstream(int devnum, char *fpgadata, size_t size, + bitstream_type bstype) +{ + int ret_val; + int flags = 0; + + ret_val = fpga_load(devnum, (void *)fpgadata, size, bstype, flags); + + /* + * Enable the HPS to FPGA bridges when FPGA load is completed + * successfully. This is to ensure the FPGA is accessible + * by the HPS. + */ + if (!ret_val) { + printf("Enable FPGA bridges\n"); + do_bridge_reset(1, ~0); + } + + return ret_val; +} +#endif + static int altera_validate(Altera_desc *desc, const char *fn) { if (!desc) {