4 Nov
2016
4 Nov
'16
12:25 p.m.
On Thu, Nov 03, 2016 at 03:35:02PM +0530, Lokesh Vutla wrote:
Only a certain set of PLLM/D values are recommended to configure the DDR at the required speeds for a given clock input frequency. Updating these values as specified in Data Sheet[1] Table 5-18
[1] http://www.ti.com/lit/ds/symlink/66ak2g02.pdf
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
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Tom