On Thu, 2014-08-07 at 16:59 -0300, Allan Fislor wrote:
On Thu, Aug 7, 2014 at 7:49 AM, Allan Fislor allan.fislor@gmail.com wrote:
On Wed, Aug 6, 2014 at 3:58 PM, Scott Wood scottwood@freescale.com wrote:
On Tue, 2014-08-05 at 16:48 -0300, Allan Fislor wrote:
Hi all,
I have a custom Freescale QorIQ P1020 board, with a serial NOR Flash (eSPI bus) and a NAND Flash (eLBC/FCM bus). Im booting from the NOR flash.
The old NAND (512 bytes page size) was working perfectly, so I swapped for another with 2k bytes page size.
I changed in the config file:
CONFIG_SYS_NAND_OR_PRELIM: added OR_FCM_PGS option
CONFIG_SYS_NAND_BLOCK_SIZE: set to (128 * 1024)
But this new NAND flash does not work. If I enter the command "nand erase.chip", all sectors appears with bad block.
Are the timings correct for your new NAND chip?
My eLBC is at 25MHz, I also tried 50MHz and 100MHz.
My current OR options are: OR_FCM_PGS | OR_FCM_CSCT | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_TRLX | OR_FCM_EHTR
I tried some combinations, without success.
What do you see if you dump the raw NAND contents?
=> nand dump 0 Page 00000000 dump: 30 30 30 30 30 30 30 30 30 20 20 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 (all zeros) 00 00 00 00 00 00 00 08 00 00 00 00 00 00 00 00 (all zeros)
OOB: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Have you seen this behavior with more than one instance of the new flash chip type?
With 2k page-size I only tested this PN: MT29F2G08ABAEAWP
And others boards with this same NAND, have the same behavior.
Cheers,
-- Allan
I got a NAND from ST-Micro, with 2k page-size. It works perfectly! And it accepts a lot of OR timings combination.
I think is something related specifically to Micron....
I don't know what the cause of the problem you're seeing is, but MT29F2G08ABAEAWP is not a good match for P1020 because it requires 4 bits of ECC per 528 bytes. P1020 has eLBC which is only capable of one bit correction per 512 bytes. So you'd need to either use software ECC, or enable support for the NAND chip's internal ECC.
-Scott