
24 Aug
2015
24 Aug
'15
7:40 p.m.
On Monday, August 24, 2015 at 11:51:46 AM, Marek Vasut wrote:
This fix makes sure that the ISWGRP0 and ISWGRP1 registers are correctly inited. In case those registers are not initialized, it is not possible to access the registers synthesised in the FPGA through the bridges. Any such access produces data abort.
Signed-off-by: Marek Vasut marex@denx.de Cc: Dinh Nguyen dinguyen@opensource.altera.com
Since this fixes an actual issue, applied.
Best regards, Marek Vasut