Rename ca_tsel_wr_select_n to tsel_wr_select_ca_n based on the bsp code.
No functionality change.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com Signed-off-by: YouMin Chen cym@rock-chips.com --- drivers/ram/rockchip/sdram_rk3399.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 3ec32bdbc0..bdb46a0128 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -160,7 +160,7 @@ static void set_ds_odt(const struct chan_info *chan,
u32 tsel_idle_en, tsel_wr_en, tsel_rd_en; u32 tsel_idle_select_p, tsel_wr_select_dq_p, tsel_rd_select_p; - u32 ca_tsel_wr_select_p, ca_tsel_wr_select_n; + u32 ca_tsel_wr_select_p, tsel_wr_select_ca_n; u32 tsel_idle_select_n, tsel_wr_select_dq_n, tsel_rd_select_n; u32 reg_value;
@@ -172,7 +172,7 @@ static void set_ds_odt(const struct chan_info *chan,
tsel_rd_select_n = PHY_DRV_ODT_240; tsel_wr_select_dq_n = PHY_DRV_ODT_40; - ca_tsel_wr_select_n = PHY_DRV_ODT_40; + tsel_wr_select_ca_n = PHY_DRV_ODT_40; tsel_idle_select_n = PHY_DRV_ODT_240; } else if (params->base.dramtype == LPDDR3) { tsel_rd_select_p = PHY_DRV_ODT_240; @@ -182,7 +182,7 @@ static void set_ds_odt(const struct chan_info *chan,
tsel_rd_select_n = PHY_DRV_ODT_HI_Z; tsel_wr_select_dq_n = PHY_DRV_ODT_34_3; - ca_tsel_wr_select_n = PHY_DRV_ODT_48; + tsel_wr_select_ca_n = PHY_DRV_ODT_48; tsel_idle_select_n = PHY_DRV_ODT_HI_Z; } else { tsel_rd_select_p = PHY_DRV_ODT_240; @@ -192,7 +192,7 @@ static void set_ds_odt(const struct chan_info *chan,
tsel_rd_select_n = PHY_DRV_ODT_240; tsel_wr_select_dq_n = PHY_DRV_ODT_34_3; - ca_tsel_wr_select_n = PHY_DRV_ODT_34_3; + tsel_wr_select_ca_n = PHY_DRV_ODT_34_3; tsel_idle_select_n = PHY_DRV_ODT_240; }
@@ -228,7 +228,7 @@ static void set_ds_odt(const struct chan_info *chan, clrsetbits_le32(&denali_phy[391], 0xffffff, reg_value);
/* phy_adr_tsel_select_ 8bits DENALI_PHY_544/672/800 offset_0 */ - reg_value = ca_tsel_wr_select_n | (ca_tsel_wr_select_p << 0x4); + reg_value = tsel_wr_select_ca_n | (ca_tsel_wr_select_p << 0x4); clrsetbits_le32(&denali_phy[544], 0xff, reg_value); clrsetbits_le32(&denali_phy[672], 0xff, reg_value); clrsetbits_le32(&denali_phy[800], 0xff, reg_value);