Hi Simon,
Thanks for reviewing.
On 18 July 2015 at 15:38, Simon Glass sjg@chromium.org wrote:
Hi Peter,
On 8 July 2015 at 09:57, Peter Griffin peter.griffin@linaro.org wrote:
HiKey is the first 96boards consumer edition compliant board. It
features a hi6220
SoC which has eight ARM A53 cpu's.
This initial port adds support for: -
- Serial
- eMMC / sd card
- USB
- GPIO
It has been tested with Arm Trusted Firmware running u-boot as the BL33
executable.
Notes:
eMMC has been tested with basic reading of eMMC partition intto DDR. I
have not
tested writing / erasing. Due to lack of clock control it won't be running in the most performant high speed mode.
SD card slot has been tested for reading and booting kernels into DDR. It is also currently used for saving the u-boot enviroment.
USB has been tested with ASIX networking adapter to tftpboot kernels into DDR. On v2015.07-rc2 dhcp now works, and also usb mass storage is enumerated correctly.
GPIO has been tested using gpio toggle GPIO4_1-3 to flash LEDs.
Basic SoC datasheet can be found here: - https://github.com/96boards/documentation/blob/master/hikey/ Hi6220V100_Multi-Mode_Application_Processor_Function_Description.pdf
Board schematic can be found here: - https://github.com/96boards/documentation/blob/master/hikey/ 96Boards-Hikey-Rev-A1.pdf
Signed-off-by: Peter Griffin peter.griffin@linaro.org
arch/arm/Kconfig | 8 + board/hisilicon/hikey/Kconfig | 15 ++ board/hisilicon/hikey/Makefile | 8 + board/hisilicon/hikey/hikey.c | 415
+++++++++++++++++++++++++++++++++++++++++
configs/hikey_defconfig | 5 + include/configs/hikey.h | 168 +++++++++++++++++ 6 files changed, 619 insertions(+) create mode 100644 board/hisilicon/hikey/Kconfig create mode 100644 board/hisilicon/hikey/Makefile create mode 100644 board/hisilicon/hikey/hikey.c create mode 100644 configs/hikey_defconfig create mode 100644 include/configs/hikey.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2985e6e..d0b7939 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -721,6 +721,13 @@ config TARGET_LS2085ARDB development platform that supports the QorIQ LS2085A Layerscape Architecture processor.
+config TARGET_HIKEY
bool "Support HiKey 96boards Consumer Edition Platform"select ARM64helpSupport for HiKey 96boards platform. It features a HI6220SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM.config TARGET_LS1021AQDS bool "Support ls1021aqds" select CPU_V7 @@ -865,6 +872,7 @@ source "board/Marvell/gplugd/Kconfig" source "board/armadeus/apf27/Kconfig" source "board/armltd/vexpress/Kconfig" source "board/armltd/vexpress64/Kconfig" +source "board/hisilicon/hikey/Kconfig" source "board/bachmann/ot1200/Kconfig" source "board/balloon3/Kconfig" source "board/barco/platinum/Kconfig" diff --git a/board/hisilicon/hikey/Kconfig
b/board/hisilicon/hikey/Kconfig
new file mode 100644 index 0000000..f7f1055 --- /dev/null +++ b/board/hisilicon/hikey/Kconfig @@ -0,0 +1,15 @@ +if TARGET_HIKEY
+config SYS_BOARD
default "hikey"+config SYS_VENDOR
default "hisilicon"+config SYS_SOC
default "hi6220"+config SYS_CONFIG_NAME
default "hikey"+endif diff --git a/board/hisilicon/hikey/Makefile
b/board/hisilicon/hikey/Makefile
new file mode 100644 index 0000000..d4ec8c7 --- /dev/null +++ b/board/hisilicon/hikey/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +#
+obj-y := hikey.o diff --git a/board/hisilicon/hikey/hikey.c
b/board/hisilicon/hikey/hikey.c
new file mode 100644 index 0000000..bd5c409 --- /dev/null +++ b/board/hisilicon/hikey/hikey.c @@ -0,0 +1,415 @@ +/*
- (C) Copyright 2015 Linaro
- Peter Griffin peter.griffin@linaro.org
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <common.h> +#include <dm.h> +#include <malloc.h> +#include <errno.h>
nit: errno.h should go above malloc.h
Fixed in v3
+#include <netdev.h> +#include <asm/io.h> +#include <asm-generic/gpio.h> +#include <asm/arch/gpio.h> +#include <asm/arch/dwmmc.h> +#include <asm/arch/hi6220.h> +#include <asm/arch/hi6553.h>
+#ifdef CONFIG_DM_GPIO
Isn't that always defined? Probably don't need this #ifdef. Also can you add a TODO to drop this table in favour of device tree?
#ifdef removed and TODO added in v3
+static const struct hikey_gpio_platdata hi6220_gpio[] = {
{ 0, HI6220_GPIO_BASE(0)},{ 1, HI6220_GPIO_BASE(1)},{ 2, HI6220_GPIO_BASE(2)},{ 3, HI6220_GPIO_BASE(3)},{ 4, HI6220_GPIO_BASE(4)},{ 5, HI6220_GPIO_BASE(5)},{ 6, HI6220_GPIO_BASE(6)},{ 7, HI6220_GPIO_BASE(7)},{ 8, HI6220_GPIO_BASE(8)},{ 9, HI6220_GPIO_BASE(9)},{ 10, HI6220_GPIO_BASE(10)},{ 11, HI6220_GPIO_BASE(11)},{ 12, HI6220_GPIO_BASE(12)},{ 13, HI6220_GPIO_BASE(13)},{ 14, HI6220_GPIO_BASE(14)},{ 15, HI6220_GPIO_BASE(15)},{ 16, HI6220_GPIO_BASE(16)},{ 17, HI6220_GPIO_BASE(17)},{ 18, HI6220_GPIO_BASE(18)},{ 19, HI6220_GPIO_BASE(19)},+};
+U_BOOT_DEVICES(hi6220_gpios) = {
{ "gpio_hi6220", &hi6220_gpio[0] },{ "gpio_hi6220", &hi6220_gpio[1] },{ "gpio_hi6220", &hi6220_gpio[2] },{ "gpio_hi6220", &hi6220_gpio[3] },{ "gpio_hi6220", &hi6220_gpio[4] },{ "gpio_hi6220", &hi6220_gpio[5] },{ "gpio_hi6220", &hi6220_gpio[6] },{ "gpio_hi6220", &hi6220_gpio[7] },{ "gpio_hi6220", &hi6220_gpio[8] },{ "gpio_hi6220", &hi6220_gpio[9] },{ "gpio_hi6220", &hi6220_gpio[10] },{ "gpio_hi6220", &hi6220_gpio[11] },{ "gpio_hi6220", &hi6220_gpio[12] },{ "gpio_hi6220", &hi6220_gpio[13] },{ "gpio_hi6220", &hi6220_gpio[14] },{ "gpio_hi6220", &hi6220_gpio[15] },{ "gpio_hi6220", &hi6220_gpio[16] },{ "gpio_hi6220", &hi6220_gpio[17] },{ "gpio_hi6220", &hi6220_gpio[18] },{ "gpio_hi6220", &hi6220_gpio[19] },+}; +#endif
+DECLARE_GLOBAL_DATA_PTR;
+#define EYE_PATTERN 0x70533483
+static void init_usb_and_picophy(void) +{
unsigned int data;/* enable USB clock */writel(PERI_CLK0_USBOTG, PERI_SC_PERIPH_CLK0_EN);do {data = readl(PERI_SC_PERIPH_CLK0_STAT);} while ((data & PERI_CLK0_USBOTG) == 0);/* take usb IPs out of reset */writel(PERI_RST0_USBOTG_BUS | PERI_RST0_POR_PICOPHY |PERI_RST0_USBOTG | PERI_RST0_USBOTG_32K,PERI_SC_PERIPH_RST0_DIS);do {data = readl(PERI_SC_PERIPH_RST0_STAT);data &= PERI_RST0_USBOTG_BUS | PERI_RST0_POR_PICOPHY |PERI_RST0_USBOTG | PERI_RST0_USBOTG_32K;} while (data);/*CTRL 5*/data = readl(PERI_SC_PERIPH_CTRL5);data &= ~PERI_CTRL5_PICOPHY_BC_MODE;data |= PERI_CTRL5_USBOTG_RES_SEL | PERI_CTRL5_PICOPHY_ACAENB;data |= 0x300;writel(data, PERI_SC_PERIPH_CTRL5);/*CTRL 4*//* configure USB PHY */data = readl(PERI_SC_PERIPH_CTRL4);/* make PHY out of low power mode */data &= ~PERI_CTRL4_PICO_SIDDQ;data &= ~PERI_CTRL4_PICO_OGDISABLE;data |= PERI_CTRL4_PICO_VBUSVLDEXTSEL |PERI_CTRL4_PICO_VBUSVLDEXT;
writel(data, PERI_SC_PERIPH_CTRL4);writel(EYE_PATTERN, PERI_SC_PERIPH_CTRL8);mdelay(5);+}
+static int sd_card_detect(void) +{
int ret;/* configure GPIO8 as nopull */writel(0, 0xf8001830);gpio_request(8, "SD CD");gpio_direction_input(8);ret = gpio_get_value(8);if (!ret) {printf("%s: SD card present\n", __func__);return 1;}printf("%s: SD card not present\n", __func__);return 0;+}
+static void mmc1_setup_pinmux(void) +{
/* switch pinmux to SD */writel(0, 0xf701000c);writel(0, 0xf7010010);writel(0, 0xf7010014);writel(0, 0xf7010018);writel(0, 0xf701001c);writel(0, 0xf7010020);/* input, 16mA or 12mA */writel(0x64, 0xf701080c);writel(0x54, 0xf7010810);writel(0x54, 0xf7010814);writel(0x54, 0xf7010818);writel(0x54, 0xf701081c);writel(0x54, 0xf7010820);Should define a struct for this peripheral.
In v3 I've added a minimal pinmux driver which I've reverse engineered by looking at the Linux code.
Sadly the Linux pinctrl settings don't actually work for the sd card slot and it hangs the board. I've debugged this to not setting BIT(2) on the pull down/up/drive registers.
I don't have any documentation on the register bit fields only the the existing code which makes things difficult :(
sd_card_detect();+}
+static void mmc1_init_pll(void) +{
uint32_t data;/* select SYSPLL as the source of MMC1 *//* select SYSPLL as the source of MUX1 (SC_CLK_SEL0) */writel(1 << 11 | 1 << 27, PERI_SC_CLK0_SEL);What are 11 and 27? Should they have an enum?
Ideally yes, but unfortunately I don't have any documentation for the register. All I know for sure is it doesn't work without it!
do {data = readl(PERI_SC_CLK0_SEL);} while (!(data & (1 << 11)));/* select MUX1 as the source of MUX2 (SC_CLK_SEL0) */writel(1 << 30, PERI_SC_CLK0_SEL);do {data = readl(PERI_SC_CLK0_SEL);} while (data & (1 << 14));Repeating code here and below - how about a function to enable a given clock?
I've added a clock_enable and clock_disable function in V3 and removed this code duplication.
writel((1 << 1), PERI_SC_PERIPH_CLK0_EN);do {data = readl(PERI_SC_PERIPH_CLK0_STAT);} while (!(data & (1 << 1)));data = readl(PERI_SC_PERIPH_CLK12_EN);data |= 1 << 2;writel(data, PERI_SC_PERIPH_CLK12_EN);do {/* 1.2GHz / 50 = 24MHz */writel(0x31 | (1 << 7), PERI_SC_CLKCFG8BIT2);data = readl(PERI_SC_CLKCFG8BIT2);} while ((data & 0x31) != 0x31);+}
+static void mmc1_reset_clk(void) +{
unsigned int data;/* disable mmc1 bus clock */writel(PERI_CLK0_MMC1, PERI_SC_PERIPH_CLK0_DIS);do {data = readl(PERI_SC_PERIPH_CLK0_STAT);} while (data & PERI_CLK0_MMC1);/* enable mmc1 bus clock */writel(PERI_CLK0_MMC1, PERI_SC_PERIPH_CLK0_EN);do {data = readl(PERI_SC_PERIPH_CLK0_STAT);} while (!(data & PERI_CLK0_MMC1));/* reset mmc1 clock domain */writel(PERI_RST0_MMC1, PERI_SC_PERIPH_RST0_EN);/* bypass mmc1 clock phase */data = readl(PERI_SC_PERIPH_CTRL2);data |= 3 << 2;writel(data, PERI_SC_PERIPH_CTRL2);/* disable low power */data = readl(PERI_SC_PERIPH_CTRL13);data |= 1 << 4;writel(data, PERI_SC_PERIPH_CTRL13);do {data = readl(PERI_SC_PERIPH_RST0_STAT);} while (!(data & PERI_RST0_MMC1));/* unreset mmc0 clock domain */writel(PERI_RST0_MMC1, PERI_SC_PERIPH_RST0_DIS);do {data = readl(PERI_SC_PERIPH_RST0_STAT);} while (data & PERI_RST0_MMC1);+}
+/* PMU SSI is the IP that maps the external PMU hi6553 registers as IO
*/
+static void hi6220_pmussi_init(void) +{
uint32_t data;/* Take PMUSSI out of reset */writel(ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_PMUSSI_N,ALWAYSON_SC_PERIPH_RST4_DIS);do {data = readl(ALWAYSON_SC_PERIPH_RST4_STAT);} while (data & ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_PMUSSI_N);/* set PMU SSI clock latency for read operation */data = readl(ALWAYSON_SC_MCU_SUBSYS_CTRL3);data &= ~ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_MASK;data |= ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_3;writel(data, ALWAYSON_SC_MCU_SUBSYS_CTRL3);/* enable PMUSSI clock */data = ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_PMUSSI_CCPU |ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_PMUSSI_MCU;writel(data, ALWAYSON_SC_PERIPH_CLK5_EN);data = ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_PMUSSI;writel(data, ALWAYSON_SC_PERIPH_CLK4_EN);/* Output high to PMIC on PWR_HOLD_GPIO0_0 */gpio_request(0, "PWR_HOLD_GPIO0_0");gpio_direction_output(0, 1);+}
+uint8_t hi6553_readb(unsigned int offset) +{
return readb((u8 *)(unsigned long)HI6220_PMUSSI_BASE + (offset<< 2));
+}
+void hi6553_writeb(unsigned int offset, uint8_t value) +{
writeb(value, (u8 *)(unsigned long)HI6220_PMUSSI_BASE + (offset<< 2));
+}
+static void hikey_hi6553_init(void) +{
int data;hi6553_writeb(HI6553_PERI_EN_MARK, 0x1e);hi6553_writeb(HI6553_NP_REG_ADJ1, 0);data = HI6553_DISABLE6_XO_CLK_CONN | HI6553_DISABLE6_XO_CLK_NFC |HI6553_DISABLE6_XO_CLK_RF1 | HI6553_DISABLE6_XO_CLK_RF2;hi6553_writeb(HI6553_DISABLE6_XO_CLK, data);/* configure BUCK0 & BUCK1 */hi6553_writeb(HI6553_BUCK01_CTRL2, 0x5e);hi6553_writeb(HI6553_BUCK0_CTRL7, 0x10);hi6553_writeb(HI6553_BUCK1_CTRL7, 0x10);hi6553_writeb(HI6553_BUCK0_CTRL5, 0x1e);hi6553_writeb(HI6553_BUCK1_CTRL5, 0x1e);hi6553_writeb(HI6553_BUCK0_CTRL1, 0xfc);hi6553_writeb(HI6553_BUCK1_CTRL1, 0xfc);/* configure BUCK2 */hi6553_writeb(HI6553_BUCK2_REG1, 0x4f);hi6553_writeb(HI6553_BUCK2_REG5, 0x99);hi6553_writeb(HI6553_BUCK2_REG6, 0x45);mdelay(1);hi6553_writeb(HI6553_VSET_BUCK2_ADJ, 0x22);mdelay(1);/* configure BUCK3 */hi6553_writeb(HI6553_BUCK3_REG3, 0x02);hi6553_writeb(HI6553_BUCK3_REG5, 0x99);hi6553_writeb(HI6553_BUCK3_REG6, 0x41);hi6553_writeb(HI6553_VSET_BUCK3_ADJ, 0x02);mdelay(1);/* configure BUCK4 */hi6553_writeb(HI6553_BUCK4_REG2, 0x9a);hi6553_writeb(HI6553_BUCK4_REG5, 0x99);hi6553_writeb(HI6553_BUCK4_REG6, 0x45);/* configure LDO20 */hi6553_writeb(HI6553_LDO20_REG_ADJ, 0x50);hi6553_writeb(HI6553_NP_REG_CHG, 0x0f);hi6553_writeb(HI6553_CLK_TOP0, 0x06);hi6553_writeb(HI6553_CLK_TOP3, 0xc0);hi6553_writeb(HI6553_CLK_TOP4, 0x00);/* configure LDO7 & LDO10 for SD slot */data = hi6553_readb(HI6553_LDO7_REG_ADJ);data = (data & 0xf8) | 0x2;hi6553_writeb(HI6553_LDO7_REG_ADJ, data);mdelay(5);/* enable LDO7 */hi6553_writeb(HI6553_ENABLE2_LDO1_8, 1 << 6);mdelay(5);data = hi6553_readb(HI6553_LDO10_REG_ADJ);data = (data & 0xf8) | 0x5;hi6553_writeb(HI6553_LDO10_REG_ADJ, data);mdelay(5);/* enable LDO10 */hi6553_writeb(HI6553_ENABLE3_LDO9_16, 1 << 1);mdelay(5);/* select 32.764KHz */hi6553_writeb(HI6553_CLK19M2_600_586_EN, 0x01);This should go in a PMIC driver. Ideally most of this would happen automatically if the voltages are in the device tree, but since you don't have one, I suggest just moving this code into the driver.
Ok I've done as you suggested and added a simple simple pmic driver in v3. From a practical PoV this means you can now dump the pmic regs using the pmic * commands, which might be helpful to somebody.
+}
+int misc_init_r(void) +{
init_usb_and_picophy();return 0;+}
+int board_init(void) +{
gd->flags = 0;Drop that.
Fixed in v3
icache_enable();Should happen in generic ARM code at start-up?
Yes Rob also pointed this out, I've removed it in V3.
return 0;+}
+#ifdef CONFIG_GENERIC_MMC
+static int init_dwmmc(void) +{
int ret;+#ifdef CONFIG_DWMMC
/* mmc0 pinmux and clocks are already configured by ATF */ret = hi6220_dwmci_add_port(0, HI6220_MMC0_BASE, 8);if (ret)printf("%s: Error adding eMMC port\n", __func__);/* take mmc1 (sd slot) out of reset, configure clocks andpinmuxing */
mmc1_init_pll();mmc1_reset_clk();mmc1_setup_pinmux();ret |= hi6220_dwmci_add_port(1, HI6220_MMC1_BASE, 4);if (ret)printf("%s: Error adding SD port\n", __func__);+#endif
return ret;+}
+int board_mmc_init(bd_t *bis) +{
int ret;/* init the pmussi ip */hi6220_pmussi_init();/* init the hi6553 pmic */hikey_hi6553_init();/* add the eMMC and sd ports */ret = init_dwmmc();if (ret)debug("init_dwmmc failed\n");return ret;+} +#endif
+int dram_init(void) +{
gd->ram_size = PHYS_SDRAM_1_SIZE;return 0;+}
+void dram_init_banksize(void) +{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;+}
+/* Use the Watchdog to cause reset */ +void reset_cpu(ulong addr) +{
/* TODO program the watchdog */+} diff --git a/configs/hikey_defconfig b/configs/hikey_defconfig new file mode 100644 index 0000000..50baf22 --- /dev/null +++ b/configs/hikey_defconfig @@ -0,0 +1,5 @@ +# 96boards HiKey +CONFIG_ARM=y +CONFIG_TARGET_HIKEY=y +CONFIG_SHOW_BOOT_PROGRESS=y
I don't think this works yet - there is no Kconfig for it. You can put it in your hikey.h file.
Ok, I've removed in V3, as not much use if it doesn't work.
+CONFIG_NET=y diff --git a/include/configs/hikey.h b/include/configs/hikey.h new file mode 100644 index 0000000..303b857 --- /dev/null +++ b/include/configs/hikey.h @@ -0,0 +1,168 @@ +/*
- (C) Copyright 2015 Linaro
- Peter Griffin peter.griffin@linaro.org
- Configuration for HiKey 96boards CE. Parts were derived from other
ARM
- configurations.
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef __HIKEY_AEMV8A_H +#define __HIKEY_AEMV8A_H
+/* We use generic board for hikey */ +#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_REMAKE_ELF
+#define CONFIG_SUPPORT_RAW_INITRD
+/* Cache Definitions */ +#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_IDENT_STRING "hikey"
+/* Flat Device Tree Definitions */ +#define CONFIG_OF_LIBFDT
+/* Physical Memory Map */
+/* CONFIG_SYS_TEXT_BASE needs to align with where ATF loads bl33.bin */ +#define CONFIG_SYS_TEXT_BASE 0x35000000
+#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 0x00000000
+/* 1008 MB (the last 16Mb are secured for TrustZone by ATF*/ +#define PHYS_SDRAM_1_SIZE 0x3f000000 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE +
0x7fff0)
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x80000)
+/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY (19000000)
+/* Generic Interrupt Controller Definitions */ +#define GICD_BASE (0xf6801000)
Don't need () around simple constants
Fixed in V3
+#define GICC_BASE (0xf6802000)
+/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20))
+/* PL011 Serial Configuration */ +#define CONFIG_PL011_SERIAL
+#define CONFIG_PL011_CLOCK 19200000 +#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0} +#define CONFIG_CONS_INDEX 0
Again this need to be device tree soon.
Yes ok. Also we wish to enable additional UARTS on the low speed connector. In v3 in the pinmux driver I've added code for the additional UARTs.
I'm also being sent an expansion board which brings out the UARTs on the lowspeed connector, so I can test this :)
+#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_SERIAL0 0xF8015000
+#define CONFIG_CMD_USB +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_DWC2 +#define CONFIG_USB_DWC2_REG_ADDR 0xF72C0000 +/*#define CONFIG_DWC2_DFLT_SPEED_FULL*/ +#define CONFIG_DWC2_ENABLE_DYNAMIC_FIFO
+#define CONFIG_USB_STORAGE +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_SMSC95XX +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_MISC_INIT_R +#endif
+#define CONFIG_HIKEY_GPIO +#define CONFIG_DM_GPIO +#define CONFIG_CMD_GPIO +#define CONFIG_DM
+/* SD/MMC configuration */ +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC +#define CONFIG_DWMMC +#define CONFIG_HIKEY_DWMMC +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_CMD_MMC
+#define CONFIG_FS_EXT4 +#define CONFIG_FS_FAT
+/* Command line configuration */ +#define CONFIG_MENU +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_BDI +#define CONFIG_CMD_UNZIP +#define CONFIG_CMD_PXE +#define CONFIG_CMD_ENV +#define CONFIG_CMD_IMI +#define CONFIG_CMD_LOADB +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_SAVEENV +#define CONFIG_CMD_RUN +#define CONFIG_CMD_BOOTD +#define CONFIG_CMD_ECHO +#define CONFIG_CMD_SOURCE
+#define CONFIG_MAC_PARTITION +#define CONFIG_MTD_PARTITIONS
+/* BOOTP options */ +#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_CMD_NET
+#include <config_distro_defaults.h>
+/* Initial environment variables */
+/*
- Defines where the kernel and FDT exist in NOR flash and where it will
- be copied into DRAM
- */
+#define CONFIG_EXTRA_ENV_SETTINGS \
"kernel_name=Image\0" \"kernel_addr=0x0000000\0" \"fdt_name=hi6220-hikey.dtb\0" \"fdt_addr=0x0300000\0" \"max_fdt=0x100000\0" \"fdt_high=0xffffffffffffffff\0" \"initrd_high=0xffffffffffffffff\0" \+/* Assume we boot with root on the first partition of a USB stick */ +#define CONFIG_BOOTARGS "console=ttyAMA0,115200n8
/dev/mmcblk0p7 rw "
+/* Copy the kernel and FDT to DRAM memory and boot */ +#define CONFIG_BOOTCOMMAND "booti $kernel_addr_r - $fdt_addr_r"
+#define CONFIG_BOOTDELAY 2
+/* Preserve enviroment onto sd card */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 1 +#define CONFIG_SYS_MMC_ENV_PART 0 +#define CONFIG_ENV_OFFSET 0x0 +#define CONFIG_ENV_SIZE 0x1000 +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET +
CONFIG_ENV_SIZE)
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer
Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)+#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_MAXARGS 64 /* max command args */
+#define CONFIG_SYS_NO_FLASH
+#endif /* __HIKEY_AEMV8A_H */
1.9.1
Regards, Simon
regards,
Peter.