The DDR PHY settings no longer depend on the DRAM size. Drop the argument from the init function.
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---
arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c | 3 +-- arch/arm/mach-uniphier/dram/ddrphy-regs.h | 3 +-- arch/arm/mach-uniphier/dram/umc-ph1-ld4.c | 4 ++-- arch/arm/mach-uniphier/dram/umc-ph1-pro4.c | 12 ++++-------- arch/arm/mach-uniphier/dram/umc-ph1-sld8.c | 4 ++-- 5 files changed, 10 insertions(+), 16 deletions(-)
diff --git a/arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c b/arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c index 27be1cc..ef1941e 100644 --- a/arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c +++ b/arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c @@ -9,8 +9,7 @@
#include "ddrphy-regs.h"
-int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size, - bool ddr3plus) +int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, bool ddr3plus) { u32 tmp;
diff --git a/arch/arm/mach-uniphier/dram/ddrphy-regs.h b/arch/arm/mach-uniphier/dram/ddrphy-regs.h index a466118..87f6d0d 100644 --- a/arch/arm/mach-uniphier/dram/ddrphy-regs.h +++ b/arch/arm/mach-uniphier/dram/ddrphy-regs.h @@ -170,8 +170,7 @@ struct ddrphy { #define DDRPHY_BASE(ch, phy) (0x5bc01000 + 0x200000 * (ch) + 0x1000 * (phy))
#ifndef __ASSEMBLY__ -int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size, - bool ddr3plus); +int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, bool ddr3plus); void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank); int ddrphy_training(struct ddrphy __iomem *phy); #endif diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c b/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c index 957a38f..bee3ef4 100644 --- a/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c +++ b/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c @@ -113,14 +113,14 @@ static int umc_init_sub(int freq, int size_ch0, int size_ch1, bool ddr3plus)
writel(0x00000101, dramcont0 + UMC_DIOCTLA);
- ph1_ld4_ddrphy_init(phy0_0, freq, size_ch0, ddr3plus); + ph1_ld4_ddrphy_init(phy0_0, freq, ddr3plus);
ddrphy_prepare_training(phy0_0, 0); ddrphy_training(phy0_0);
writel(0x00000101, dramcont1 + UMC_DIOCTLA);
- ph1_ld4_ddrphy_init(phy1_0, freq, size_ch1, ddr3plus); + ph1_ld4_ddrphy_init(phy1_0, freq, ddr3plus);
ddrphy_prepare_training(phy1_0, 1); ddrphy_training(phy1_0); diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c b/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c index 877f5ef..0a2485e 100644 --- a/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c +++ b/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c @@ -138,32 +138,28 @@ int ph1_pro4_umc_init(const struct uniphier_board_data *bd)
writel(0x00000101, dramcont0 + UMC_DIOCTLA);
- ph1_ld4_ddrphy_init(phy0_0, bd->dram_freq, bd->dram_ch[0].size, - bd->dram_ddr3plus); + ph1_ld4_ddrphy_init(phy0_0, bd->dram_freq, bd->dram_ddr3plus);
ddrphy_prepare_training(phy0_0, 0); ddrphy_training(phy0_0);
writel(0x00000103, dramcont0 + UMC_DIOCTLA);
- ph1_ld4_ddrphy_init(phy0_1, bd->dram_freq, bd->dram_ch[0].size, - bd->dram_ddr3plus); + ph1_ld4_ddrphy_init(phy0_1, bd->dram_freq, bd->dram_ddr3plus);
ddrphy_prepare_training(phy0_1, 1); ddrphy_training(phy0_1);
writel(0x00000101, dramcont1 + UMC_DIOCTLA);
- ph1_ld4_ddrphy_init(phy1_0, bd->dram_freq, bd->dram_ch[1].size, - bd->dram_ddr3plus); + ph1_ld4_ddrphy_init(phy1_0, bd->dram_freq, bd->dram_ddr3plus);
ddrphy_prepare_training(phy1_0, 0); ddrphy_training(phy1_0);
writel(0x00000103, dramcont1 + UMC_DIOCTLA);
- ph1_ld4_ddrphy_init(phy1_1, bd->dram_freq, bd->dram_ch[1].size, - bd->dram_ddr3plus); + ph1_ld4_ddrphy_init(phy1_1, bd->dram_freq, bd->dram_ddr3plus);
ddrphy_prepare_training(phy1_1, 1); ddrphy_training(phy1_1); diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c b/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c index a27f91f..73ad934 100644 --- a/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c +++ b/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c @@ -97,14 +97,14 @@ static int umc_init_sub(int freq, int size_ch0, int size_ch1, bool ddr3plus)
writel(0x00000101, dramcont0 + UMC_DIOCTLA);
- ph1_ld4_ddrphy_init(phy0_0, freq, size_ch0, ddr3plus); + ph1_ld4_ddrphy_init(phy0_0, freq, ddr3plus);
ddrphy_prepare_training(phy0_0, 0); ddrphy_training(phy0_0);
writel(0x00000101, dramcont1 + UMC_DIOCTLA);
- ph1_ld4_ddrphy_init(phy1_0, freq, size_ch1, ddr3plus); + ph1_ld4_ddrphy_init(phy1_0, freq, ddr3plus);
ddrphy_prepare_training(phy1_0, 1); ddrphy_training(phy1_0);