On Thu, Jan 26, 2017 at 6:23 AM, Simon Glass sjg@chromium.org wrote:
On 18 January 2017 at 14:44, Maxim Sloyko maxims@google.com wrote:
Clock Driver
This driver is ast2500-specific and is not compatible with earlier versions of this chip. The differences are not that big, but they are in somewhat random places, so making it compatible with ast2400 is not worth the effort at the moment.
SDRAM MC driver
The driver is very ast2500-specific and is completely incompatible with previous versions of the chip.
The memory controller is very poorly documented by Aspeed in the datasheet, with any mention of the whole range of registers missing. The initialization procedure has been basically taken from Aspeed SDK, where it is implemented in assembly. Here it is rewritten in C, with very limited understanding of what exactly it is doing.
Changes in v4:
- Expanded AST2500 EVB description in Kconfig
- Added docstrings for ast_get_clk() and ast_get_scu()
- Fixed include file ordering
- Added docstring for ast2500_get_uart_clk_rate
- Use dev_get_addr_ptr
- Use WDT helper function to reset memory controller
Changes in v3: None Changes in v2: None Changes in v1:
- Merge together all patches related to ast2500 specific drivers
- Add Copyright statement to all c/h files
- Use DT include from Linux Kernel, Add U-Boot specific modifications in ast2500-u-boot.dtsi
Reviewed-by: Tom Rini trini@konsulko.com
Signed-off-by: Maxim Sloyko maxims@google.com
arch/arm/dts/ast2500-u-boot.dtsi | 53 +++ arch/arm/dts/ast2500.dtsi | 174 +++++++++ arch/arm/include/asm/arch-aspeed/scu_ast2500.h | 125 +++++++ arch/arm/include/asm/arch-aspeed/sdram_ast2500.h | 138 ++++++++ arch/arm/mach-aspeed/Kconfig | 2 + arch/arm/mach-aspeed/Makefile | 1 + arch/arm/mach-aspeed/ast2500/Kconfig | 14 + arch/arm/mach-aspeed/ast2500/Makefile | 1 + arch/arm/mach-aspeed/ast2500/clk_ast2500.c | 30 ++ arch/arm/mach-aspeed/ast2500/sdram_ast2500.c | 432 +++++++++++++++++++++++ drivers/clk/Makefile | 2 + drivers/clk/aspeed/Makefile | 7 + drivers/clk/aspeed/clk_ast2500.c | 265 ++++++++++++++ include/dt-bindings/clock/ast2500-scu.h | 29 ++ 14 files changed, 1273 insertions(+) create mode 100644 arch/arm/dts/ast2500-u-boot.dtsi create mode 100644 arch/arm/dts/ast2500.dtsi create mode 100644 arch/arm/include/asm/arch-aspeed/scu_ast2500.h create mode 100644 arch/arm/include/asm/arch-aspeed/sdram_ast2500.h create mode 100644 arch/arm/mach-aspeed/ast2500/Kconfig create mode 100644 arch/arm/mach-aspeed/ast2500/Makefile create mode 100644 arch/arm/mach-aspeed/ast2500/clk_ast2500.c create mode 100644 arch/arm/mach-aspeed/ast2500/sdram_ast2500.c create mode 100644 drivers/clk/aspeed/Makefile create mode 100644 drivers/clk/aspeed/clk_ast2500.c create mode 100644 include/dt-bindings/clock/ast2500-scu.h
Reviewed-by: Simon Glass sjg@chromium.org
A few nits for later:
I think it is better to define a shifted mask:
#define SDRAM_REFRESH_PERIOD_SHIFT 8 #define SDRAM_REFRESH_PERIOD_MASK (0xf << SDRAM_REFRESH_PERIOD_SHIFT)
What is CONFIG_DUALX8_RAM for? Can this be encoded in the device tree?
This should be used when the board has two DRAM PHY chips connected to single controller. At least that's my understanding. We don't use that configuration on any of our boards, so probably it would be easier just to remove it.
Regards, Simon