Since the card device is set the proper timing after speed mode switch is completed, host driver can get ddr_mode from timing parameter. So drop the antiquated ddr_mode.
Signed-off-by: Ziyuan Xu xzy.xu@rock-chips.com ---
cmd/mmc.c | 2 +- drivers/mmc/dw_mmc.c | 2 +- drivers/mmc/fsl_esdhc.c | 4 ++-- drivers/mmc/mmc.c | 3 +-- drivers/mmc/uniphier-sd.c | 4 ++-- drivers/mmc/xenon_sdhci.c | 6 +++--- include/mmc.h | 1 - 7 files changed, 10 insertions(+), 12 deletions(-)
diff --git a/cmd/mmc.c b/cmd/mmc.c index f83032e..ef05fa5 100644 --- a/cmd/mmc.c +++ b/cmd/mmc.c @@ -38,7 +38,7 @@ static void print_mmcinfo(struct mmc *mmc) print_size(mmc->capacity, "\n");
printf("Bus Width: %d-bit%s\n", mmc->bus_width, - mmc->ddr_mode ? " DDR" : ""); + mmc_card_ddr(mmc) ? " DDR" : "");
puts("Erase Group Size: "); print_size(((u64)mmc->erase_grp_size) << 9, "\n"); diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index baf2280..7e9ffc2 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -432,7 +432,7 @@ static int dwmci_set_ios(struct mmc *mmc) dwmci_writel(host, DWMCI_CTYPE, ctype);
regs = dwmci_readl(host, DWMCI_UHS_REG); - if (mmc->ddr_mode) + if (mmc_card_ddr(mmc)) regs |= DWMCI_DDR_MODE; else regs &= ~DWMCI_DDR_MODE; diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index f3c6358..5a6942e 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -400,7 +400,7 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) #if defined(CONFIG_FSL_USDHC) esdhc_write32(®s->mixctrl, (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F) - | (mmc->ddr_mode ? XFERTYP_DDREN : 0)); + | (mmc_card_ddr(mmc) ? XFERTYP_DDREN : 0)); esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000); #else esdhc_write32(®s->xfertyp, xfertyp); @@ -541,7 +541,7 @@ static void set_sysctl(struct mmc *mmc, uint clock) if ((sdhc_clk / (div * pre_div)) <= clock) break;
- pre_div >>= mmc->ddr_mode ? 2 : 1; + pre_div >>= mmc_card_ddr(mmc) ? 2 : 1; div -= 1;
clk = (pre_div << 8) | (div << 4); diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index bebf8f3..d47cfe6 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -210,7 +210,7 @@ int mmc_set_blocklen(struct mmc *mmc, int len) { struct mmc_cmd cmd;
- if (mmc->ddr_mode) + if (mmc_card_ddr(mmc)) return 0;
cmd.cmdidx = MMC_CMD_SET_BLOCKLEN; @@ -1926,7 +1926,6 @@ int mmc_start_init(struct mmc *mmc) if (err) return err; #endif - mmc->ddr_mode = 0; mmc_set_bus_width(mmc, 1); mmc_set_clock(mmc, 1); mmc_set_timing(mmc, MMC_TIMING_LEGACY); diff --git a/drivers/mmc/uniphier-sd.c b/drivers/mmc/uniphier-sd.c index 7f20ef1..ac7359b 100644 --- a/drivers/mmc/uniphier-sd.c +++ b/drivers/mmc/uniphier-sd.c @@ -532,7 +532,7 @@ static void uniphier_sd_set_ddr_mode(struct uniphier_sd_priv *priv, u32 tmp;
tmp = readl(priv->regbase + UNIPHIER_SD_IF_MODE); - if (mmc->ddr_mode) + if (mmc_card_ddr(mmc)) tmp |= UNIPHIER_SD_IF_MODE_DDR; else tmp &= ~UNIPHIER_SD_IF_MODE_DDR; @@ -599,7 +599,7 @@ static int uniphier_sd_set_ios(struct udevice *dev) int ret;
dev_dbg(dev, "clock %uHz, DDRmode %d, width %u\n", - mmc->clock, mmc->ddr_mode, mmc->bus_width); + mmc->clock, mmc_card_ddr(mmc), mmc->bus_width);
ret = uniphier_sd_set_bus_width(priv, mmc); if (ret) diff --git a/drivers/mmc/xenon_sdhci.c b/drivers/mmc/xenon_sdhci.c index f0a33c1..7685e15 100644 --- a/drivers/mmc/xenon_sdhci.c +++ b/drivers/mmc/xenon_sdhci.c @@ -237,7 +237,7 @@ static void xenon_mmc_phy_set(struct sdhci_host *host) sdhci_writew(host, var, SDHCI_CLOCK_CONTROL);
var = sdhci_readl(host, EMMC_PHY_FUNC_CONTROL); - if (host->mmc->ddr_mode) { + if (mmc_card_ddr(host->mmc)) { var |= (DQ_DDR_MODE_MASK << DQ_DDR_MODE_SHIFT) | CMD_DDR_MODE; } else { var &= ~((DQ_DDR_MODE_MASK << DQ_DDR_MODE_SHIFT) | @@ -329,7 +329,7 @@ static void xenon_sdhci_set_ios_post(struct sdhci_host *host) if (IS_SD(host->mmc)) { /* SD/SDIO */ if (pwr_18v) { - if (host->mmc->ddr_mode) + if (mmc_card_ddr(host->mmc)) priv->timing = MMC_TIMING_UHS_DDR50; else if (speed <= 25000000) priv->timing = MMC_TIMING_UHS_SDR25; @@ -343,7 +343,7 @@ static void xenon_sdhci_set_ios_post(struct sdhci_host *host) } } else { /* eMMC */ - if (host->mmc->ddr_mode) + if (mmc_card_ddr(host->mmc)) priv->timing = MMC_TIMING_MMC_DDR52; else if (speed <= 26000000) priv->timing = MMC_TIMING_LEGACY; diff --git a/include/mmc.h b/include/mmc.h index a2ef986..bde8b37 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -523,7 +523,6 @@ struct mmc { char op_cond_pending; /* 1 if we are waiting on an op_cond command */ char init_in_progress; /* 1 if we have done mmc_start_init() */ char preinit; /* start init as early as possible */ - int ddr_mode; #ifdef CONFIG_DM_MMC struct udevice *dev; /* Device for this MMC controller */ #endif