On Tue, Jan 28, 2020 at 3:44 PM Marcel Ziswiler marcel@ziswiler.com wrote:
From: Igor Opaniuk igor.opaniuk@toradex.com
This adds initial minimal support for the Toradex Verdin iMX8M Mini Quad 2GB WB IT V1.0A module. They are now strapped to boot from eFuses which are factory fused to properly boot from their on-module eMMC. U-Boot supports booting from the on-module eMMC only, SDP support is disabled for now due to missing i.MX 8M Mini USB support.
Functionality wise the following is known to be working:
- eMMC, 8-bit and 4-bit MMC/SD card slots
- Ethernet
- GPIOs
- I2C
Boot sequence is: SPL ---> ATF (TF-A) ---> U-boot proper
ATF, U-boot proper and u-boot.dtb images are packed into a FIT image, loaded by SPL.
Boot: U-Boot SPL 2020.01-00187-gd411d164e5 (Jan 26 2020 - 04:47:26 +0100) Normal Boot Trying to boot from MMC1 NOTICE: Configuring TZASC380 NOTICE: RDC off NOTICE: BL31: v2.0(release):rel_imx_4.14.98_2.3.0-0-g09c5cc994-dirty NOTICE: BL31: Built : 01:11:41, Jan 25 2020 NOTICE: sip svc init
U-Boot 2020.01-00187-gd411d164e5 (Jan 26 2020 - 04:47:26 +0100)
CPU: Freescale i.MX8MMQ rev1.0 at 0 MHz Reset cause: POR DRAM: 2 GiB MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2 Loading Environment from MMC... OK In: serial Out: serial Err: serial Model: Toradex Verdin iMX8M Mini Quad 2GB Wi-Fi / BT IT V1.0A, Serial# 06535149 Net: eth0: ethernet@30be0000 Hit any key to stop autoboot: 0 Verdin iMX8MM #
Signed-off-by: Igor Opaniuk igor.opaniuk@toradex.com Signed-off-by: Max Krummenacher max.krummenacher@toradex.com Signed-off-by: Marcel Ziswiler marcel.ziswiler@toradex.com
Reviewed-by: Oleksandr Suvorov oleksandr.suvorov@toradex.com
Changes in v3:
- Drop AG resp. Inc. in copyright notices as adviced by our legal.
- Use pin names from the linux-next pinfunc sync as suggested by Oleksandr.
Changes in v2:
- Further clean-up as announced on the mailing list.
arch/arm/dts/Makefile | 1 + arch/arm/dts/imx8mm-verdin-u-boot.dtsi | 103 ++ arch/arm/dts/imx8mm-verdin.dts | 1007 ++++++++++ arch/arm/mach-imx/imx8m/Kconfig | 7 + board/toradex/verdin-imx8mm/Kconfig | 30 + board/toradex/verdin-imx8mm/Makefile | 11 + board/toradex/verdin-imx8mm/imximage.cfg | 16 + board/toradex/verdin-imx8mm/lpddr4_timing.c | 1850 +++++++++++++++++++ board/toradex/verdin-imx8mm/spl.c | 180 ++ board/toradex/verdin-imx8mm/verdin-imx8mm.c | 73 + configs/verdin-imx8mm_defconfig | 98 + include/configs/verdin-imx8mm.h | 128 ++ 12 files changed, 3504 insertions(+) create mode 100644 arch/arm/dts/imx8mm-verdin-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mm-verdin.dts create mode 100644 board/toradex/verdin-imx8mm/Kconfig create mode 100644 board/toradex/verdin-imx8mm/Makefile create mode 100644 board/toradex/verdin-imx8mm/imximage.cfg create mode 100644 board/toradex/verdin-imx8mm/lpddr4_timing.c create mode 100644 board/toradex/verdin-imx8mm/spl.c create mode 100644 board/toradex/verdin-imx8mm/verdin-imx8mm.c create mode 100644 configs/verdin-imx8mm_defconfig create mode 100644 include/configs/verdin-imx8mm.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 9303beb2f5..895d405922 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -718,6 +718,7 @@ dtb-$(CONFIG_ARCH_IMX8) += \
dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mm-evk.dtb \
imx8mm-verdin.dtb \ imx8mn-ddr4-evk.dtb \ imx8mq-evk.dtb \ imx8mp-evk.dtbdiff --git a/arch/arm/dts/imx8mm-verdin-u-boot.dtsi b/arch/arm/dts/imx8mm-verdin-u-boot.dtsi new file mode 100644 index 0000000000..d091577a96 --- /dev/null +++ b/arch/arm/dts/imx8mm-verdin-u-boot.dtsi @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/*
- Copyright 2020 Toradex
- */
+&aips1 {
u-boot,dm-spl;u-boot,dm-pre-reloc;+};
+&aips2 {
u-boot,dm-spl;+};
+&aips3 {
u-boot,dm-spl;+};
+&clk {
u-boot,dm-spl;u-boot,dm-pre-reloc;/delete-property/ assigned-clocks;/delete-property/ assigned-clock-parents;/delete-property/ assigned-clock-rates;+};
+&gpio1 {
u-boot,dm-spl;+};
+&gpio2 {
u-boot,dm-spl;+};
+&gpio3 {
u-boot,dm-spl;+};
+&gpio4 {
u-boot,dm-spl;+};
+&gpio5 {
u-boot,dm-spl;+};
+&i2c1 {
u-boot,dm-spl;+};
+&iomuxc {
u-boot,dm-spl;+};
+&osc_24m {
u-boot,dm-spl;u-boot,dm-pre-reloc;+};
+&pinctrl_i2c1 {
u-boot,dm-spl;+};
+&pinctrl_pmic {
u-boot,dm-spl;+};
+&pinctrl_uart1 {
u-boot,dm-spl;+};
+&pinctrl_usdhc2 {
u-boot,dm-spl;+};
+&{/soc@0} {
u-boot,dm-pre-reloc;u-boot,dm-spl;+};
+&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} {
u-boot,dm-spl;+};
+&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} {
u-boot,dm-spl;+};
+&uart1 {
u-boot,dm-spl;+};
+&usdhc1 {
u-boot,dm-spl;+};
+&usdhc2 {
u-boot,dm-spl;+};
+&usdhc3 {
u-boot,dm-spl;+}; diff --git a/arch/arm/dts/imx8mm-verdin.dts b/arch/arm/dts/imx8mm-verdin.dts new file mode 100644 index 0000000000..2980053e82 --- /dev/null +++ b/arch/arm/dts/imx8mm-verdin.dts @@ -0,0 +1,1007 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/*
- Copyright 2020 Toradex
- */
+/dts-v1/;
+#include <dt-bindings/usb/pd.h> +#include "imx8mm.dtsi"
+/ {
model = "Toradex Verdin iMX8M Mini Quad/DualLite";compatible = "toradex,verdin-imx8mm", "fsl,imx8mm";chosen {stdout-path = &uart1;};/* fixed clock dedicated to SPI CAN controller */clk20m: oscillator {compatible = "fixed-clock";#clock-cells = <0>;clock-frequency = <20000000>;};reg_ethphy: regulator-ethphy {compatible = "regulator-fixed";enable-active-high;gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>;off-on-delay = <500000>;pinctrl-names = "default";pinctrl-0 = <&pinctrl_reg_eth>;regulator-boot-on;regulator-max-microvolt = <3300000>;regulator-min-microvolt = <3300000>;regulator-name = "V3.3_ETH";startup-delay-us = <200000>;};reg_usb_otg1_vbus: regulator-usb-otg1 {compatible = "regulator-fixed";enable-active-high;/* Verdin USB1_EN */gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;pinctrl-names = "default";pinctrl-0 = <&pinctrl_reg_usb1_en>;regulator-name = "usb_otg1_vbus";regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;};reg_usb_otg2_vbus: regulator-usb-otg2 {compatible = "regulator-fixed";enable-active-high;/* Verdin USB2_EN */gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;pinctrl-names = "default";pinctrl-0 = <&pinctrl_reg_usb2_en>;regulator-name = "usb_otg2_vbus";regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;};reg_usdhc2_vmmc: regulator-usdhc2 {compatible = "regulator-fixed";enable-active-high;gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>;pinctrl-names = "default";pinctrl-0 = <&pinctrl_usdhc2_pwr_en>;regulator-name = "V3.3_SD";regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;startup-delay-us = <2000>;};reg_wifi_en: regulator-wifi-en {compatible = "regulator-fixed";enable-active-high;gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>;pinctrl-names = "default";pinctrl-0 = <&pinctrl_wifi_pwr_en>;regulator-name = "V3.3_WI-FI";regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;startup-delay-us = <2000>;};+};
+&A53_0 {
arm-supply = <&buck2_reg>;+};
+&clk {
assigned-clocks = <&clk IMX8MM_AUDIO_PLL1>, <&clk IMX8MM_AUDIO_PLL2>;assigned-clock-rates = <786432000>, <722534400>;+};
+/* Verdin SPI_1 */ +&ecspi2 {
#address-cells = <1>;#size-cells = <0>;pinctrl-names = "default";pinctrl-0 = <&pinctrl_ecspi2>;cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;status = "okay";spidev20: spidev@0 {compatible = "toradex,evalspi";reg = <0>;spi-max-frequency = <10000000>;status = "okay";};+};
+/* On-module CAN controller 1 & 2 */ +&ecspi3 {
#address-cells = <1>;#size-cells = <0>;cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>,<&gpio1 5 GPIO_ACTIVE_LOW>;/* This property is required, even if marked as obsolete in the doku */fsl,spi-num-chipselects = <2>;pinctrl-names = "default";pinctrl-0 = <&pinctrl_ecspi3>;status = "okay";can1: can@0 {compatible = "microchip,mcp2517fd";clocks = <&clk20m>;gpio-controller;interrupt-parent = <&gpio1>;interrupts = <6 IRQ_TYPE_EDGE_FALLING>;microchip,clock-allways-on;microchip,clock-out-div = <1>;pinctrl-names = "default";pinctrl-0 = <&pinctrl_can1_int>;reg = <0>;spi-max-frequency = <2000000>;};can2: can@1 {compatible = "microchip,mcp2517fd";clocks = <&clk20m>;gpio-controller;interrupt-parent = <&gpio1>;interrupts = <7 IRQ_TYPE_EDGE_FALLING>;pinctrl-names = "default";pinctrl-0 = <&pinctrl_can2_int>;reg = <1>;spi-max-frequency = <2000000>;};+};
+&fec1 {
fsl,magic-packet;fsl,rgmii_rxc_dly;fsl,rgmii_txc_dly;phy-handle = <ðphy0>;phy-mode = "rgmii";phy-supply = <®_ethphy>;pinctrl-names = "default", "sleep";pinctrl-0 = <&pinctrl_fec1>;pinctrl-1 = <&pinctrl_fec1_sleep>;status = "okay";mdio {#address-cells = <1>;#size-cells = <0>;ethphy0: ethernet-phy@7 {compatible = "ethernet-phy-ieee802.3-c22";interrupt-parent = <&gpio1>;interrupts = <10 IRQ_TYPE_LEVEL_LOW>;micrel,led-mode = <0>;reg = <7>;};};+};
+&gpio4 {
/** The SE050 security element may be driven via I2C from user space.* The element itself is enabled here as it has no kernel driver.*/se050_ena {gpio-hog;gpios = <19 GPIO_ACTIVE_HIGH>;line-name = "SE050_ENABLE";output-high;pinctrl-names = "default";pinctrl-0 = <&pinctrl_se050_ena>;};+};
+/* On-module I2C */ +&i2c1 {
clock-frequency = <400000>;pinctrl-names = "default";pinctrl-0 = <&pinctrl_i2c1>;status = "okay";pmic@4b {compatible = "rohm,bd71840", "rohm,bd71837";bd71837,pmic-buck2-uses-i2c-dvs;bd71837,pmic-buck2-dvs-voltage = <1000000>, <900000>, <0>; /* VDD_ARM: Run-Idle */gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>;/* PMIC BD71837 PMIC_nINT GPIO1_IO3 */pinctrl-0 = <&pinctrl_pmic>;reg = <0x4b>;gpo {rohm,drv = <0x0C>; /* 0b0000_1100 all gpos with cmos output mode */};regulators {buck1_reg: BUCK1 {regulator-always-on;regulator-boot-on;regulator-compatible = "buck1";regulator-max-microvolt = <1300000>;regulator-min-microvolt = <700000>;regulator-ramp-delay = <1250>;};buck2_reg: BUCK2 {regulator-always-on;regulator-boot-on;regulator-compatible = "buck2";regulator-max-microvolt = <1300000>;regulator-min-microvolt = <700000>;regulator-ramp-delay = <1250>;};buck5_reg: BUCK5 {regulator-always-on;regulator-boot-on;regulator-compatible = "buck5";regulator-max-microvolt = <1350000>;regulator-min-microvolt = <700000>;};buck6_reg: BUCK6 {regulator-always-on;regulator-boot-on;regulator-compatible = "buck6";regulator-max-microvolt = <3300000>;regulator-min-microvolt = <3000000>;};buck7_reg: BUCK7 {regulator-always-on;regulator-boot-on;regulator-compatible = "buck7";regulator-max-microvolt = <1995000>;regulator-min-microvolt = <1605000>;};buck8_reg: BUCK8 {regulator-always-on;regulator-boot-on;regulator-compatible = "buck8";regulator-max-microvolt = <1400000>;regulator-min-microvolt = <800000>;};ldo1_reg: LDO1 {regulator-always-on;regulator-boot-on;regulator-compatible = "ldo1";regulator-max-microvolt = <3300000>;regulator-min-microvolt = <3000000>;};ldo2_reg: LDO2 {regulator-always-on;regulator-boot-on;regulator-compatible = "ldo2";regulator-max-microvolt = <900000>;regulator-min-microvolt = <900000>;};ldo3_reg: LDO3 {regulator-always-on;regulator-boot-on;regulator-compatible = "ldo3";regulator-max-microvolt = <3300000>;regulator-min-microvolt = <1800000>;};ldo4_reg: LDO4 {regulator-always-on;regulator-boot-on;regulator-compatible = "ldo4";regulator-max-microvolt = <1800000>;regulator-min-microvolt = <900000>;};ldo5_reg: LDO5 {regulator-compatible = "ldo5";regulator-max-microvolt = <3300000>;regulator-min-microvolt = <3300000>;};ldo6_reg: LDO6 {regulator-always-on;regulator-boot-on;regulator-compatible = "ldo6";regulator-max-microvolt = <1800000>;regulator-min-microvolt = <900000>;};};};/* Epson RX8130 real time clock on carrier board */rtc@32 {compatible = "epson,rx8130";reg = <0x32>;};adc@34 {compatible = "maxim,max11607";reg = <0x34>;vcc-supply = <&ldo5_reg>;};eeprom@50 {compatible = "st,24c02";pagesize = <16>;reg = <0x50>;};+};
+/* Verdin I2C_2_DSI */ +&i2c2 {
clock-frequency = <10000>;pinctrl-names = "default";pinctrl-0 = <&pinctrl_i2c2>;status = "okay";+};
+/* Verdin I2C_3_HDMI N/A */
+/* Verdin I2C_4_CSI */ +&i2c3 {
clock-frequency = <400000>;pinctrl-names = "default";pinctrl-0 = <&pinctrl_i2c3>;status = "okay";+};
+/* Verdin I2C_1 */ +&i2c4 {
clock-frequency = <400000>;pinctrl-names = "default";pinctrl-0 = <&pinctrl_i2c4>;status = "okay";/* Audio Codec */wm8904_1a: codec@1a {compatible = "wlf,wm8904";#sound-dai-cells = <0>;clocks = <&clk IMX8MM_CLK_SAI2_ROOT>;clock-names = "mclk";reg = <0x1a>;};gpio_expander_21: gpio-expander@21 {compatible = "nxp,pcal6416";#gpio-cells = <2>;gpio-controller;reg = <0x21>;};/* Current measurement into module VCC */hwmon@40 {compatible = "ti,ina219";reg = <0x40>;shunt-resistor = <10000>;status = "okay";};/* EEPROM on MIPI-DSI to HDMI adapter */eeprom_50: eeprom@50 {compatible = "st,24c02";pagesize = <16>;reg = <0x50>;};/* EEPROM on Verdin Development board */eeprom_57: eeprom@57 {compatible = "st,24c02";pagesize = <16>;reg = <0x57>;};+};
+/* Verdin PWM_3_DSI */ +&pwm1 {
pinctrl-names = "default";pinctrl-0 = <&pinctrl_pwm_1>;#pwm-cells = <3>;status = "okay";+};
+/* Verdin PWM_1 */ +&pwm2 {
pinctrl-names = "default";pinctrl-0 = <&pinctrl_pwm_2>;#pwm-cells = <3>;status = "okay";+};
+/* Verdin PWM_2 */ +&pwm3 {
pinctrl-names = "default";pinctrl-0 = <&pinctrl_pwm_3>;#pwm-cells = <3>;status = "okay";+};
+/* Verdin UART_3, Console/Debug UART */ +&uart1 {
fsl,uart-has-rtscts;pinctrl-names = "default";pinctrl-0 = <&pinctrl_uart1>;status = "okay";+};
+/* Verdin UART_1 */ +&uart2 {
pinctrl-names = "default";pinctrl-0 = <&pinctrl_uart2>;fsl,uart-has-rtscts;status = "okay";+};
+/* Verdin UART_2 */ +&uart3 {
pinctrl-names = "default";pinctrl-0 = <&pinctrl_uart3>;fsl,uart-has-rtscts;status = "okay";+};
+/* Verdin UART_4 */ +/*
- resource allocated to M4 by default, must not be accessed from A-35 or you
- get an OOPS
- */
+&uart4 {
pinctrl-names = "default";pinctrl-0 = <&pinctrl_uart4>;status = "disabled";+};
+/* Verdin USB_1 */ +&usbotg1 {
dr_mode = "otg";picophy,dc-vol-level-adjust = <7>;picophy,pre-emp-curr-control = <3>;vbus-supply = <®_usb_otg1_vbus>;status = "okay";+};
+/* Verdin USB_2 */ +&usbotg2 {
dr_mode = "host";picophy,dc-vol-level-adjust = <7>;picophy,pre-emp-curr-control = <3>;vbus-supply = <®_usb_otg2_vbus>;status = "okay";+};
+/* On-module eMMC */ +&usdhc1 {
bus-width = <8>;keep-power-in-suspend;non-removable;pinctrl-names = "default", "state_100mhz", "state_200mhz";pinctrl-0 = <&pinctrl_usdhc1>;pinctrl-1 = <&pinctrl_usdhc1_100mhz>;pinctrl-2 = <&pinctrl_usdhc1_200mhz>;pm-ignore-notify;status = "okay";/* TODO Strobe */+};
+/* Verdin SD_1 */ +&usdhc2 {
bus-width = <4>;cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;pinctrl-names = "default", "state_100mhz", "state_200mhz";pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>;pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>;pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>;vmmc-supply = <®_usdhc2_vmmc>;status = "okay";+};
+/* On-module Wi-Fi */ +&usdhc3 {
bus-width = <4>;non-removable;pinctrl-names = "default", "state_100mhz", "state_200mhz";pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_wifi_ctrl>;pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_wifi_ctrl>;pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_wifi_ctrl>;vmmc-supply = <®_wifi_en>;status = "okay";+};
+&wdog1 {
fsl,ext-reset-output;pinctrl-names = "default";pinctrl-0 = <&pinctrl_wdog>;status = "okay";+};
+&iomuxc {
pinctrl-names = "default";pinctrl-0 = <&pinctrl_dsi_bkl_en>, <&pinctrl_gpio1>, <&pinctrl_gpio2>,<&pinctrl_gpio3>, <&pinctrl_gpio4>, <&pinctrl_gpio5>,<&pinctrl_gpio6>, <&pinctrl_gpio7>, <&pinctrl_gpio8>,<&pinctrl_gpio_hog1>, <&pinctrl_gpio_hog2>,<&pinctrl_gpio_hog3>, <&pinctrl_gpio_hpd>;pinctrl_can1_int: can1intgrp {fsl,pins = <MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x1c4>;};pinctrl_can2_int: can2intgrp {fsl,pins = <MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x1c4>;};pinctrl_ctrl_force_off_moci: ctrlforceoffgrp {fsl,pins = <MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x1c4 /* SODIMM 250 */>;};pinctrl_dsi_bkl_en: dsi_bkl_en {fsl,pins = <MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x1c4 /* SODIMM 21 */>;};pinctrl_ecspi2: ecspi2grp {fsl,pins = <MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x1c4 /* SODIMM 198 */MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x4 /* SODIMM 200 */MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x4 /* SODIMM 196 */MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x1c4 /* SODIMM 202 */>;};pinctrl_ecspi3: ecspi3grp {fsl,pins = <MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x1c4MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x4MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x4MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x1c4MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x1c4>;};pinctrl_fec1: fec1grp {fsl,pins = <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1fMX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1fMX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1fMX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1fMX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1fMX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1fMX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x1c4>;};pinctrl_fec1_sleep: fec1-sleepgrp {fsl,pins = <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21 0x1fMX8MM_IOMUXC_ENET_TD1_GPIO1_IO20 0x1fMX8MM_IOMUXC_ENET_TD2_GPIO1_IO19 0x1fMX8MM_IOMUXC_ENET_TD3_GPIO1_IO18 0x1fMX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 0x1fMX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x1fMX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x184>;};pinctrl_flexspi0: flexspi0grp {fsl,pins = <MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 /* SODIMM 52 */MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 /* SODIMM 54 */MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x82 /* SODIMM 64 */MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 /* SODIMM 56 */MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 /* SODIMM 58 */MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 /* SODIMM 60 */MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 /* SODIMM 62 */MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x82 /* SODIMM 66 */>;};/* (MEZ_)GPIO_1 shared with (MEZ_)DSI_1_INT# on Verdin Development Board */pinctrl_gpio1: gpio1grp {fsl,pins = <MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x184 /* SODIMM 206 */>;};pinctrl_gpio2: gpio2grp {fsl,pins = <MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x184 /* SODIMM 208 */>;};pinctrl_gpio3: gpio3grp {fsl,pins = <MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x184 /* SODIMM 210 */>;};pinctrl_gpio4: gpio4grp {fsl,pins = <MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x184 /* SODIMM 212 */>;};pinctrl_gpio5: gpio5grp {fsl,pins = <MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x184 /* SODIMM 216 */>;};pinctrl_gpio6: gpio6grp {fsl,pins = <MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x184 /* SODIMM 218 */>;};pinctrl_gpio7: gpio7grp {fsl,pins = <MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x184 /* SODIMM 220 */>;};pinctrl_gpio8: gpio8grp {fsl,pins = <MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x184 /* SODIMM 222 */>;};pinctrl_gpio_hog1: gpiohog1grp {fsl,pins = <MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x1c4 /* SODIMM 88 */MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x1c4 /* SODIMM 90 */MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x1c4 /* SODIMM 92 */MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x1c4 /* SODIMM 94 */MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x1c4 /* SODIMM 96 */MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x1c4 /* SODIMM 100 */MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x1c4 /* SODIMM 102 */MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x1c4 /* SODIMM 104 */MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x1c4 /* SODIMM 106 */MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x1c4 /* SODIMM 108 */MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x1c4 /* SODIMM 112 */MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x1c4 /* SODIMM 114 */MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x1c4 /* SODIMM 116 */MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1c4 /* SODIMM 118 */MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x1c4 /* SODIMM 120 */>;};pinctrl_gpio_hog2: gpiohog2grp {fsl,pins = <MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x1c4 /* SODIMM 91 */>;};pinctrl_gpio_hog3: gpiohog3grp {fsl,pins = <MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x1c4 /* SODIMM 157 */MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4 /* SODIMM 187 */>;};/* (MEZ_)DSI_1_INT# shared with (MEZ_)GPIO_1 on Verdin Development Board */pinctrl_gpio_hpd: gpiohpdgrp {fsl,pins = <MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x184 /* SODIMM 17 */>;};/* On-module I2C */pinctrl_i2c1: i2c1grp {fsl,pins = <MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c6MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c6>;};/* Verdin I2C_4_CSI */pinctrl_i2c2: i2c2grp {fsl,pins = <MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c6 /* SODIMM 55 */MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c6 /* SODIMM 53 */>;};/* Verdin I2C_2_DSI */pinctrl_i2c3: i2c3grp {fsl,pins = <MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c6 /* SODIMM 95 */MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c6 /* SODIMM 93 */>;};/* Verdin I2C_1 */pinctrl_i2c4: i2c4grp {fsl,pins = <MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c6 /* SODIMM 14 */MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c6 /* SODIMM 12 */>;};pinctrl_pcie0: pcie0grp {fsl,pins = <MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x6 /* SODIMM 244 */MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x6 /* PMIC_EN_PCIe_CLK */>;};pinctrl_pmic: pmicirqgrp {fsl,pins = <MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41>;};pinctrl_pwm_1: pwm1grp {fsl,pins = <MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x6 /* SODIMM 19 */>;};pinctrl_pwm_2: pwm2grp {fsl,pins = <MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x6 /* SODIMM 15 */>;};pinctrl_pwm_3: pwm3grp {fsl,pins = <MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x6 /* SODIMM 16 */>;};pinctrl_reg_eth: regethgrp {fsl,pins = <MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x184>;};pinctrl_reg_usb1_en: regusb1engrp {fsl,pins = <MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x184 /* SODIMM 155 */>;};pinctrl_reg_usb2_en: regusb2engrp {fsl,pins = <MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x184 /* SODIMM 185 */>;};pinctrl_sai2: sai2grp {fsl,pins = <MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 /* SODIMM 38 */MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 /* SODIMM 36 */MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 /* SODIMM 30 */MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 /* SODIMM 34 */MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 /* SODIMM 32 */>;};pinctrl_sai5: sai5grp {fsl,pins = <MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6 /* SODIMM 48 */MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0xd6 /* SODIMM 44 */MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0xd6 /* SODIMM 42 */MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0xd6 /* SODIMM 46 */>;};pinctrl_se050_ena: se050enagrp {fsl,pins = <MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x184>;};pinctrl_uart1: uart1grp {fsl,pins = <MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x1c4 /* SODIMM 147 */MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x1c4 /* SODIMM 149 */>;};pinctrl_uart2: uart2grp {fsl,pins = <MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x1c4 /* SODIMM 133 */MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x1c4 /* SODIMM 135 */MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x1c4 /* SODIMM 131 */MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x1c4 /* SODIMM 129 */>;};pinctrl_uart3: uart3grp {fsl,pins = <MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x1c4 /* SODIMM 141 */MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x1c4 /* SODIMM 139 */MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x1c4 /* SODIMM 137 */MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x1c4 /* SODIMM 143 */>;};pinctrl_uart4: uart4grp {fsl,pins = <MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x1c4 /* SODIMM 151 */MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x1c4 /* SODIMM 153 */>;};pinctrl_usdhc1: usdhc1grp {fsl,pins = <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190>;};pinctrl_usdhc1_100mhz: usdhc1grp100mhz {fsl,pins = <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194>;};pinctrl_usdhc1_200mhz: usdhc1grp200mhz {fsl,pins = <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196>;};pinctrl_usdhc2_cd: usdhc2cdgrp {fsl,pins = <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 /* SODIMM 84 */>;};pinctrl_usdhc2_pwr_en: usdhc2pwrengrp {fsl,pins = <MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x184 /* SODIMM 76 */>;};pinctrl_usdhc2: usdhc2grp {fsl,pins = <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 /* SODIMM 78 */MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 /* SODIMM 74 */MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 /* SODIMM 80 */MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 /* SODIMM 82 */MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 /* SODIMM 70 */MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 /* SODIMM 72 */>;};pinctrl_usdhc2_100mhz: usdhc2grp100mhz {fsl,pins = <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4>;};pinctrl_usdhc2_200mhz: usdhc2grp200mhz {fsl,pins = <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6>;};pinctrl_usdhc3: usdhc3grp {fsl,pins = <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0>;};pinctrl_usdhc3_100mhz: usdhc3grp100mhz {fsl,pins = <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4>;};pinctrl_usdhc3_200mhz: usdhc3grp200mhz {fsl,pins = <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6>;};pinctrl_wdog: wdoggrp {fsl,pins = <MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6>;};pinctrl_wifi_ctrl: wifictrlgrp {fsl,pins = <MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x1c4 /* WIFI_WKUP_BT */MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x1c4 /* WIFI_W_WKUP_HOST */MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x1c4 /* WIFI_WKUP_WLAN */>;};pinctrl_wifi_i2s: wifii2sgrp {fsl,pins = <MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0xd6MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0xd6MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0xd6MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0xd6>;};pinctrl_wifi_pwr_en: wifipwrengrp {fsl,pins = <MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x184 /* PMIC_EN_WIFI */>;};+}; diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 72affb1bdc..58f1758ab6 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -50,11 +50,18 @@ config TARGET_IMX8MP_EVK select SUPPORT_SPL select IMX8M_LPDDR4
+config TARGET_VERDIN_IMX8MM
bool "Support Toradex Verdin iMX8M Mini module"select IMX8MMselect SUPPORT_SPLselect IMX8M_LPDDR4endchoice
source "board/freescale/imx8mq_evk/Kconfig" source "board/freescale/imx8mm_evk/Kconfig" source "board/freescale/imx8mn_evk/Kconfig" source "board/freescale/imx8mp_evk/Kconfig" +source "board/toradex/verdin-imx8mm/Kconfig"
endif diff --git a/board/toradex/verdin-imx8mm/Kconfig b/board/toradex/verdin-imx8mm/Kconfig new file mode 100644 index 0000000000..8a2fe98682 --- /dev/null +++ b/board/toradex/verdin-imx8mm/Kconfig @@ -0,0 +1,30 @@ +if TARGET_VERDIN_IMX8MM
+config SYS_BOARD
default "verdin-imx8mm"+config SYS_VENDOR
default "toradex"+config SYS_CONFIG_NAME
default "verdin-imx8mm"+config TDX_CFG_BLOCK
default y+config TDX_HAVE_MMC
default y+config TDX_CFG_BLOCK_DEV
default "0"+config TDX_CFG_BLOCK_PART
default "1"+# Toradex config block in eMMC, at the end of 1st "boot sector" +config TDX_CFG_BLOCK_OFFSET
default "-512"+source "board/toradex/common/Kconfig"
+endif diff --git a/board/toradex/verdin-imx8mm/Makefile b/board/toradex/verdin-imx8mm/Makefile new file mode 100644 index 0000000000..b38054254d --- /dev/null +++ b/board/toradex/verdin-imx8mm/Makefile @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright 2020 Toradex +#
+obj-y += verdin-imx8mm.o
+ifdef CONFIG_SPL_BUILD +obj-y += spl.o +obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o +endif diff --git a/board/toradex/verdin-imx8mm/imximage.cfg b/board/toradex/verdin-imx8mm/imximage.cfg new file mode 100644 index 0000000000..b8b25ff420 --- /dev/null +++ b/board/toradex/verdin-imx8mm/imximage.cfg @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*
- Copyright 2020 Toradex
- */
+#define __ASSEMBLY__
+FIT +BOOT_FROM emmc_fastboot +LOADER spl/u-boot-spl-ddr.bin 0x7E1000 +SECOND_LOADER u-boot.itb 0x40200000 0x60000
+DDR_FW lpddr4_pmu_train_1d_imem.bin +DDR_FW lpddr4_pmu_train_1d_dmem.bin +DDR_FW lpddr4_pmu_train_2d_imem.bin +DDR_FW lpddr4_pmu_train_2d_dmem.bin diff --git a/board/toradex/verdin-imx8mm/lpddr4_timing.c b/board/toradex/verdin-imx8mm/lpddr4_timing.c new file mode 100644 index 0000000000..d114abf9d6 --- /dev/null +++ b/board/toradex/verdin-imx8mm/lpddr4_timing.c @@ -0,0 +1,1850 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Copyright 2020 Toradex
- Generated code from MX8M_DDR_tool
- Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga
- DDR calibration created with mscale_ddr_tool_v210_setup.exe using
- MX8M_Mini_LPDDR4_RPA_v14 Verdin iMX8MM V1.0.xlsx as of 1. Nov. 2019.
- */
+#include <linux/kernel.h> +#include <asm/arch/ddr.h>
+struct dram_cfg_param ddr_ddrc_cfg[] = {
/** Initialize DDRC registers **/{0x3d400304, 0x1},{0x3d400030, 0x1},{0x3d400000, 0xa1080020},{0x3d400020, 0x203},{0x3d400024, 0x3a980},{0x3d400064, 0x5b00d2},{0x3d4000d0, 0xc00305ba},{0x3d4000d4, 0x940000},{0x3d4000dc, 0xd4002d},{0x3d4000e0, 0x310000},{0x3d4000e8, 0x66004d},{0x3d4000ec, 0x16004d},{0x3d400100, 0x191e1920},{0x3d400104, 0x60630},{0x3d40010c, 0xb0b000},{0x3d400110, 0xe04080e},{0x3d400114, 0x2040c0c},{0x3d400118, 0x1010007},{0x3d40011c, 0x401},{0x3d400130, 0x20600},{0x3d400134, 0xc100002},{0x3d400138, 0xd8},{0x3d400144, 0x96004b},{0x3d400180, 0x2ee0017},{0x3d400184, 0x2605b8e},{0x3d400188, 0x0},{0x3d400190, 0x497820a},{0x3d400194, 0x80303},{0x3d4001b4, 0x170a},{0x3d4001a0, 0xe0400018},{0x3d4001a4, 0xdf00e4},{0x3d4001a8, 0x80000000},{0x3d4001b0, 0x11},{0x3d4001c0, 0x1},{0x3d4001c4, 0x1},{0x3d4000f4, 0xc99},{0x3d400108, 0x70e1617},{0x3d400200, 0x1f},{0x3d40020c, 0x0},{0x3d400210, 0x1f1f},{0x3d400204, 0x80808},{0x3d400214, 0x7070707},{0x3d400218, 0x7070707},{0x3d400250, 0x29001701},{0x3d400254, 0x2c},{0x3d40025c, 0x4000030},{0x3d400264, 0x900093e7},{0x3d40026c, 0x2005574},{0x3d400400, 0x111},{0x3d400408, 0x72ff},{0x3d400494, 0x2100e07},{0x3d400498, 0x620096},{0x3d40049c, 0x1100e07},{0x3d4004a0, 0xc8012c},{0x3d402020, 0x1},{0x3d402024, 0x7d00},{0x3d402050, 0x20d040},{0x3d402064, 0xc001c},{0x3d4020dc, 0x840000},{0x3d4020e0, 0x310000},{0x3d4020e8, 0x66004d},{0x3d4020ec, 0x16004d},{0x3d402100, 0xa040305},{0x3d402104, 0x30407},{0x3d402108, 0x203060b},{0x3d40210c, 0x505000},{0x3d402110, 0x2040202},{0x3d402114, 0x2030202},{0x3d402118, 0x1010004},{0x3d40211c, 0x301},{0x3d402130, 0x20300},{0x3d402134, 0xa100002},{0x3d402138, 0x1d},{0x3d402144, 0x14000a},{0x3d402180, 0x640004},{0x3d402190, 0x3818200},{0x3d402194, 0x80303},{0x3d4021b4, 0x100},{0x3d4020f4, 0xc99},{0x3d403020, 0x1},{0x3d403024, 0x1f40},{0x3d403050, 0x20d040},{0x3d403064, 0x30007},{0x3d4030dc, 0x840000},{0x3d4030e0, 0x310000},{0x3d4030e8, 0x66004d},{0x3d4030ec, 0x16004d},{0x3d403100, 0xa010102},{0x3d403104, 0x30404},{0x3d403108, 0x203060b},{0x3d40310c, 0x505000},{0x3d403110, 0x2040202},{0x3d403114, 0x2030202},{0x3d403118, 0x1010004},{0x3d40311c, 0x301},{0x3d403130, 0x20300},{0x3d403134, 0xa100002},{0x3d403138, 0x8},{0x3d403144, 0x50003},{0x3d403180, 0x190004},{0x3d403190, 0x3818200},{0x3d403194, 0x80303},{0x3d4031b4, 0x100},{0x3d4030f4, 0xc99},{0x3d400028, 0x0},+};
+/* PHY Initialize Configuration */ +struct dram_cfg_param ddr_ddrphy_cfg[] = {
{0x100a0, 0x0},{0x100a1, 0x1},{0x100a2, 0x2},{0x100a3, 0x3},{0x100a4, 0x4},{0x100a5, 0x5},{0x100a6, 0x6},{0x100a7, 0x7},{0x110a0, 0x0},{0x110a1, 0x1},{0x110a2, 0x3},{0x110a3, 0x4},{0x110a4, 0x5},{0x110a5, 0x2},{0x110a6, 0x6},{0x110a7, 0x7},{0x120a0, 0x0},{0x120a1, 0x1},{0x120a2, 0x3},{0x120a3, 0x4},{0x120a4, 0x5},{0x120a5, 0x2},{0x120a6, 0x6},{0x120a7, 0x7},{0x130a0, 0x0},{0x130a1, 0x1},{0x130a2, 0x2},{0x130a3, 0x3},{0x130a4, 0x4},{0x130a5, 0x5},{0x130a6, 0x6},{0x130a7, 0x7},{0x1005f, 0x1ff},{0x1015f, 0x1ff},{0x1105f, 0x1ff},{0x1115f, 0x1ff},{0x1205f, 0x1ff},{0x1215f, 0x1ff},{0x1305f, 0x1ff},{0x1315f, 0x1ff},{0x11005f, 0x1ff},{0x11015f, 0x1ff},{0x11105f, 0x1ff},{0x11115f, 0x1ff},{0x11205f, 0x1ff},{0x11215f, 0x1ff},{0x11305f, 0x1ff},{0x11315f, 0x1ff},{0x21005f, 0x1ff},{0x21015f, 0x1ff},{0x21105f, 0x1ff},{0x21115f, 0x1ff},{0x21205f, 0x1ff},{0x21215f, 0x1ff},{0x21305f, 0x1ff},{0x21315f, 0x1ff},{0x55, 0x1ff},{0x1055, 0x1ff},{0x2055, 0x1ff},{0x3055, 0x1ff},{0x4055, 0x1ff},{0x5055, 0x1ff},{0x6055, 0x1ff},{0x7055, 0x1ff},{0x8055, 0x1ff},{0x9055, 0x1ff},{0x200c5, 0x19},{0x1200c5, 0x7},{0x2200c5, 0x7},{0x2002e, 0x2},{0x12002e, 0x2},{0x22002e, 0x2},{0x90204, 0x0},{0x190204, 0x0},{0x290204, 0x0},{0x20024, 0x1ab},{0x2003a, 0x0},{0x120024, 0x1ab},{0x2003a, 0x0},{0x220024, 0x1ab},{0x2003a, 0x0},{0x20056, 0x3},{0x120056, 0xa},{0x220056, 0xa},{0x1004d, 0xe00},{0x1014d, 0xe00},{0x1104d, 0xe00},{0x1114d, 0xe00},{0x1204d, 0xe00},{0x1214d, 0xe00},{0x1304d, 0xe00},{0x1314d, 0xe00},{0x11004d, 0xe00},{0x11014d, 0xe00},{0x11104d, 0xe00},{0x11114d, 0xe00},{0x11204d, 0xe00},{0x11214d, 0xe00},{0x11304d, 0xe00},{0x11314d, 0xe00},{0x21004d, 0xe00},{0x21014d, 0xe00},{0x21104d, 0xe00},{0x21114d, 0xe00},{0x21204d, 0xe00},{0x21214d, 0xe00},{0x21304d, 0xe00},{0x21314d, 0xe00},{0x10049, 0xeba},{0x10149, 0xeba},{0x11049, 0xeba},{0x11149, 0xeba},{0x12049, 0xeba},{0x12149, 0xeba},{0x13049, 0xeba},{0x13149, 0xeba},{0x110049, 0xeba},{0x110149, 0xeba},{0x111049, 0xeba},{0x111149, 0xeba},{0x112049, 0xeba},{0x112149, 0xeba},{0x113049, 0xeba},{0x113149, 0xeba},{0x210049, 0xeba},{0x210149, 0xeba},{0x211049, 0xeba},{0x211149, 0xeba},{0x212049, 0xeba},{0x212149, 0xeba},{0x213049, 0xeba},{0x213149, 0xeba},{0x43, 0x63},{0x1043, 0x63},{0x2043, 0x63},{0x3043, 0x63},{0x4043, 0x63},{0x5043, 0x63},{0x6043, 0x63},{0x7043, 0x63},{0x8043, 0x63},{0x9043, 0x63},{0x20018, 0x3},{0x20075, 0x4},{0x20050, 0x0},{0x20008, 0x2ee},{0x120008, 0x64},{0x220008, 0x19},{0x20088, 0x9},{0x200b2, 0xdc},{0x10043, 0x5a1},{0x10143, 0x5a1},{0x11043, 0x5a1},{0x11143, 0x5a1},{0x12043, 0x5a1},{0x12143, 0x5a1},{0x13043, 0x5a1},{0x13143, 0x5a1},{0x1200b2, 0xdc},{0x110043, 0x5a1},{0x110143, 0x5a1},{0x111043, 0x5a1},{0x111143, 0x5a1},{0x112043, 0x5a1},{0x112143, 0x5a1},{0x113043, 0x5a1},{0x113143, 0x5a1},{0x2200b2, 0xdc},{0x210043, 0x5a1},{0x210143, 0x5a1},{0x211043, 0x5a1},{0x211143, 0x5a1},{0x212043, 0x5a1},{0x212143, 0x5a1},{0x213043, 0x5a1},{0x213143, 0x5a1},{0x200fa, 0x1},{0x1200fa, 0x1},{0x2200fa, 0x1},{0x20019, 0x1},{0x120019, 0x1},{0x220019, 0x1},{0x200f0, 0x660},{0x200f1, 0x0},{0x200f2, 0x4444},{0x200f3, 0x8888},{0x200f4, 0x5665},{0x200f5, 0x0},{0x200f6, 0x0},{0x200f7, 0xf000},{0x20025, 0x0},{0x2002d, 0x0},{0x12002d, 0x0},{0x22002d, 0x0},{0x200c7, 0x21},{0x1200c7, 0x21},{0x2200c7, 0x21},{0x200ca, 0x24},{0x1200ca, 0x24},{0x2200ca, 0x24},+};
+/* ddr phy trained csr */ +struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
{ 0x200b2, 0x0 },{ 0x1200b2, 0x0 },{ 0x2200b2, 0x0 },{ 0x200cb, 0x0 },{ 0x10043, 0x0 },{ 0x110043, 0x0 },{ 0x210043, 0x0 },{ 0x10143, 0x0 },{ 0x110143, 0x0 },{ 0x210143, 0x0 },{ 0x11043, 0x0 },{ 0x111043, 0x0 },{ 0x211043, 0x0 },{ 0x11143, 0x0 },{ 0x111143, 0x0 },{ 0x211143, 0x0 },{ 0x12043, 0x0 },{ 0x112043, 0x0 },{ 0x212043, 0x0 },{ 0x12143, 0x0 },{ 0x112143, 0x0 },{ 0x212143, 0x0 },{ 0x13043, 0x0 },{ 0x113043, 0x0 },{ 0x213043, 0x0 },{ 0x13143, 0x0 },{ 0x113143, 0x0 },{ 0x213143, 0x0 },{ 0x80, 0x0 },{ 0x100080, 0x0 },{ 0x200080, 0x0 },{ 0x1080, 0x0 },{ 0x101080, 0x0 },{ 0x201080, 0x0 },{ 0x2080, 0x0 },{ 0x102080, 0x0 },{ 0x202080, 0x0 },{ 0x3080, 0x0 },{ 0x103080, 0x0 },{ 0x203080, 0x0 },{ 0x4080, 0x0 },{ 0x104080, 0x0 },{ 0x204080, 0x0 },{ 0x5080, 0x0 },{ 0x105080, 0x0 },{ 0x205080, 0x0 },{ 0x6080, 0x0 },{ 0x106080, 0x0 },{ 0x206080, 0x0 },{ 0x7080, 0x0 },{ 0x107080, 0x0 },{ 0x207080, 0x0 },{ 0x8080, 0x0 },{ 0x108080, 0x0 },{ 0x208080, 0x0 },{ 0x9080, 0x0 },{ 0x109080, 0x0 },{ 0x209080, 0x0 },{ 0x10080, 0x0 },{ 0x110080, 0x0 },{ 0x210080, 0x0 },{ 0x10180, 0x0 },{ 0x110180, 0x0 },{ 0x210180, 0x0 },{ 0x11080, 0x0 },{ 0x111080, 0x0 },{ 0x211080, 0x0 },{ 0x11180, 0x0 },{ 0x111180, 0x0 },{ 0x211180, 0x0 },{ 0x12080, 0x0 },{ 0x112080, 0x0 },{ 0x212080, 0x0 },{ 0x12180, 0x0 },{ 0x112180, 0x0 },{ 0x212180, 0x0 },{ 0x13080, 0x0 },{ 0x113080, 0x0 },{ 0x213080, 0x0 },{ 0x13180, 0x0 },{ 0x113180, 0x0 },{ 0x213180, 0x0 },{ 0x10081, 0x0 },{ 0x110081, 0x0 },{ 0x210081, 0x0 },{ 0x10181, 0x0 },{ 0x110181, 0x0 },{ 0x210181, 0x0 },{ 0x11081, 0x0 },{ 0x111081, 0x0 },{ 0x211081, 0x0 },{ 0x11181, 0x0 },{ 0x111181, 0x0 },{ 0x211181, 0x0 },{ 0x12081, 0x0 },{ 0x112081, 0x0 },{ 0x212081, 0x0 },{ 0x12181, 0x0 },{ 0x112181, 0x0 },{ 0x212181, 0x0 },{ 0x13081, 0x0 },{ 0x113081, 0x0 },{ 0x213081, 0x0 },{ 0x13181, 0x0 },{ 0x113181, 0x0 },{ 0x213181, 0x0 },{ 0x100d0, 0x0 },{ 0x1100d0, 0x0 },{ 0x2100d0, 0x0 },{ 0x101d0, 0x0 },{ 0x1101d0, 0x0 },{ 0x2101d0, 0x0 },{ 0x110d0, 0x0 },{ 0x1110d0, 0x0 },{ 0x2110d0, 0x0 },{ 0x111d0, 0x0 },{ 0x1111d0, 0x0 },{ 0x2111d0, 0x0 },{ 0x120d0, 0x0 },{ 0x1120d0, 0x0 },{ 0x2120d0, 0x0 },{ 0x121d0, 0x0 },{ 0x1121d0, 0x0 },{ 0x2121d0, 0x0 },{ 0x130d0, 0x0 },{ 0x1130d0, 0x0 },{ 0x2130d0, 0x0 },{ 0x131d0, 0x0 },{ 0x1131d0, 0x0 },{ 0x2131d0, 0x0 },{ 0x100d1, 0x0 },{ 0x1100d1, 0x0 },{ 0x2100d1, 0x0 },{ 0x101d1, 0x0 },{ 0x1101d1, 0x0 },{ 0x2101d1, 0x0 },{ 0x110d1, 0x0 },{ 0x1110d1, 0x0 },{ 0x2110d1, 0x0 },{ 0x111d1, 0x0 },{ 0x1111d1, 0x0 },{ 0x2111d1, 0x0 },{ 0x120d1, 0x0 },{ 0x1120d1, 0x0 },{ 0x2120d1, 0x0 },{ 0x121d1, 0x0 },{ 0x1121d1, 0x0 },{ 0x2121d1, 0x0 },{ 0x130d1, 0x0 },{ 0x1130d1, 0x0 },{ 0x2130d1, 0x0 },{ 0x131d1, 0x0 },{ 0x1131d1, 0x0 },{ 0x2131d1, 0x0 },{ 0x10068, 0x0 },{ 0x10168, 0x0 },{ 0x10268, 0x0 },{ 0x10368, 0x0 },{ 0x10468, 0x0 },{ 0x10568, 0x0 },{ 0x10668, 0x0 },{ 0x10768, 0x0 },{ 0x10868, 0x0 },{ 0x11068, 0x0 },{ 0x11168, 0x0 },{ 0x11268, 0x0 },{ 0x11368, 0x0 },{ 0x11468, 0x0 },{ 0x11568, 0x0 },{ 0x11668, 0x0 },{ 0x11768, 0x0 },{ 0x11868, 0x0 },{ 0x12068, 0x0 },{ 0x12168, 0x0 },{ 0x12268, 0x0 },{ 0x12368, 0x0 },{ 0x12468, 0x0 },{ 0x12568, 0x0 },{ 0x12668, 0x0 },{ 0x12768, 0x0 },{ 0x12868, 0x0 },{ 0x13068, 0x0 },{ 0x13168, 0x0 },{ 0x13268, 0x0 },{ 0x13368, 0x0 },{ 0x13468, 0x0 },{ 0x13568, 0x0 },{ 0x13668, 0x0 },{ 0x13768, 0x0 },{ 0x13868, 0x0 },{ 0x10069, 0x0 },{ 0x10169, 0x0 },{ 0x10269, 0x0 },{ 0x10369, 0x0 },{ 0x10469, 0x0 },{ 0x10569, 0x0 },{ 0x10669, 0x0 },{ 0x10769, 0x0 },{ 0x10869, 0x0 },{ 0x11069, 0x0 },{ 0x11169, 0x0 },{ 0x11269, 0x0 },{ 0x11369, 0x0 },{ 0x11469, 0x0 },{ 0x11569, 0x0 },{ 0x11669, 0x0 },{ 0x11769, 0x0 },{ 0x11869, 0x0 },{ 0x12069, 0x0 },{ 0x12169, 0x0 },{ 0x12269, 0x0 },{ 0x12369, 0x0 },{ 0x12469, 0x0 },{ 0x12569, 0x0 },{ 0x12669, 0x0 },{ 0x12769, 0x0 },{ 0x12869, 0x0 },{ 0x13069, 0x0 },{ 0x13169, 0x0 },{ 0x13269, 0x0 },{ 0x13369, 0x0 },{ 0x13469, 0x0 },{ 0x13569, 0x0 },{ 0x13669, 0x0 },{ 0x13769, 0x0 },{ 0x13869, 0x0 },{ 0x1008c, 0x0 },{ 0x11008c, 0x0 },{ 0x21008c, 0x0 },{ 0x1018c, 0x0 },{ 0x11018c, 0x0 },{ 0x21018c, 0x0 },{ 0x1108c, 0x0 },{ 0x11108c, 0x0 },{ 0x21108c, 0x0 },{ 0x1118c, 0x0 },{ 0x11118c, 0x0 },{ 0x21118c, 0x0 },{ 0x1208c, 0x0 },{ 0x11208c, 0x0 },{ 0x21208c, 0x0 },{ 0x1218c, 0x0 },{ 0x11218c, 0x0 },{ 0x21218c, 0x0 },{ 0x1308c, 0x0 },{ 0x11308c, 0x0 },{ 0x21308c, 0x0 },{ 0x1318c, 0x0 },{ 0x11318c, 0x0 },{ 0x21318c, 0x0 },{ 0x1008d, 0x0 },{ 0x11008d, 0x0 },{ 0x21008d, 0x0 },{ 0x1018d, 0x0 },{ 0x11018d, 0x0 },{ 0x21018d, 0x0 },{ 0x1108d, 0x0 },{ 0x11108d, 0x0 },{ 0x21108d, 0x0 },{ 0x1118d, 0x0 },{ 0x11118d, 0x0 },{ 0x21118d, 0x0 },{ 0x1208d, 0x0 },{ 0x11208d, 0x0 },{ 0x21208d, 0x0 },{ 0x1218d, 0x0 },{ 0x11218d, 0x0 },{ 0x21218d, 0x0 },{ 0x1308d, 0x0 },{ 0x11308d, 0x0 },{ 0x21308d, 0x0 },{ 0x1318d, 0x0 },{ 0x11318d, 0x0 },{ 0x21318d, 0x0 },{ 0x100c0, 0x0 },{ 0x1100c0, 0x0 },{ 0x2100c0, 0x0 },{ 0x101c0, 0x0 },{ 0x1101c0, 0x0 },{ 0x2101c0, 0x0 },{ 0x102c0, 0x0 },{ 0x1102c0, 0x0 },{ 0x2102c0, 0x0 },{ 0x103c0, 0x0 },{ 0x1103c0, 0x0 },{ 0x2103c0, 0x0 },{ 0x104c0, 0x0 },{ 0x1104c0, 0x0 },{ 0x2104c0, 0x0 },{ 0x105c0, 0x0 },{ 0x1105c0, 0x0 },{ 0x2105c0, 0x0 },{ 0x106c0, 0x0 },{ 0x1106c0, 0x0 },{ 0x2106c0, 0x0 },{ 0x107c0, 0x0 },{ 0x1107c0, 0x0 },{ 0x2107c0, 0x0 },{ 0x108c0, 0x0 },{ 0x1108c0, 0x0 },{ 0x2108c0, 0x0 },{ 0x110c0, 0x0 },{ 0x1110c0, 0x0 },{ 0x2110c0, 0x0 },{ 0x111c0, 0x0 },{ 0x1111c0, 0x0 },{ 0x2111c0, 0x0 },{ 0x112c0, 0x0 },{ 0x1112c0, 0x0 },{ 0x2112c0, 0x0 },{ 0x113c0, 0x0 },{ 0x1113c0, 0x0 },{ 0x2113c0, 0x0 },{ 0x114c0, 0x0 },{ 0x1114c0, 0x0 },{ 0x2114c0, 0x0 },{ 0x115c0, 0x0 },{ 0x1115c0, 0x0 },{ 0x2115c0, 0x0 },{ 0x116c0, 0x0 },{ 0x1116c0, 0x0 },{ 0x2116c0, 0x0 },{ 0x117c0, 0x0 },{ 0x1117c0, 0x0 },{ 0x2117c0, 0x0 },{ 0x118c0, 0x0 },{ 0x1118c0, 0x0 },{ 0x2118c0, 0x0 },{ 0x120c0, 0x0 },{ 0x1120c0, 0x0 },{ 0x2120c0, 0x0 },{ 0x121c0, 0x0 },{ 0x1121c0, 0x0 },{ 0x2121c0, 0x0 },{ 0x122c0, 0x0 },{ 0x1122c0, 0x0 },{ 0x2122c0, 0x0 },{ 0x123c0, 0x0 },{ 0x1123c0, 0x0 },{ 0x2123c0, 0x0 },{ 0x124c0, 0x0 },{ 0x1124c0, 0x0 },{ 0x2124c0, 0x0 },{ 0x125c0, 0x0 },{ 0x1125c0, 0x0 },{ 0x2125c0, 0x0 },{ 0x126c0, 0x0 },{ 0x1126c0, 0x0 },{ 0x2126c0, 0x0 },{ 0x127c0, 0x0 },{ 0x1127c0, 0x0 },{ 0x2127c0, 0x0 },{ 0x128c0, 0x0 },{ 0x1128c0, 0x0 },{ 0x2128c0, 0x0 },{ 0x130c0, 0x0 },{ 0x1130c0, 0x0 },{ 0x2130c0, 0x0 },{ 0x131c0, 0x0 },{ 0x1131c0, 0x0 },{ 0x2131c0, 0x0 },{ 0x132c0, 0x0 },{ 0x1132c0, 0x0 },{ 0x2132c0, 0x0 },{ 0x133c0, 0x0 },{ 0x1133c0, 0x0 },{ 0x2133c0, 0x0 },{ 0x134c0, 0x0 },{ 0x1134c0, 0x0 },{ 0x2134c0, 0x0 },{ 0x135c0, 0x0 },{ 0x1135c0, 0x0 },{ 0x2135c0, 0x0 },{ 0x136c0, 0x0 },{ 0x1136c0, 0x0 },{ 0x2136c0, 0x0 },{ 0x137c0, 0x0 },{ 0x1137c0, 0x0 },{ 0x2137c0, 0x0 },{ 0x138c0, 0x0 },{ 0x1138c0, 0x0 },{ 0x2138c0, 0x0 },{ 0x100c1, 0x0 },{ 0x1100c1, 0x0 },{ 0x2100c1, 0x0 },{ 0x101c1, 0x0 },{ 0x1101c1, 0x0 },{ 0x2101c1, 0x0 },{ 0x102c1, 0x0 },{ 0x1102c1, 0x0 },{ 0x2102c1, 0x0 },{ 0x103c1, 0x0 },{ 0x1103c1, 0x0 },{ 0x2103c1, 0x0 },{ 0x104c1, 0x0 },{ 0x1104c1, 0x0 },{ 0x2104c1, 0x0 },{ 0x105c1, 0x0 },{ 0x1105c1, 0x0 },{ 0x2105c1, 0x0 },{ 0x106c1, 0x0 },{ 0x1106c1, 0x0 },{ 0x2106c1, 0x0 },{ 0x107c1, 0x0 },{ 0x1107c1, 0x0 },{ 0x2107c1, 0x0 },{ 0x108c1, 0x0 },{ 0x1108c1, 0x0 },{ 0x2108c1, 0x0 },{ 0x110c1, 0x0 },{ 0x1110c1, 0x0 },{ 0x2110c1, 0x0 },{ 0x111c1, 0x0 },{ 0x1111c1, 0x0 },{ 0x2111c1, 0x0 },{ 0x112c1, 0x0 },{ 0x1112c1, 0x0 },{ 0x2112c1, 0x0 },{ 0x113c1, 0x0 },{ 0x1113c1, 0x0 },{ 0x2113c1, 0x0 },{ 0x114c1, 0x0 },{ 0x1114c1, 0x0 },{ 0x2114c1, 0x0 },{ 0x115c1, 0x0 },{ 0x1115c1, 0x0 },{ 0x2115c1, 0x0 },{ 0x116c1, 0x0 },{ 0x1116c1, 0x0 },{ 0x2116c1, 0x0 },{ 0x117c1, 0x0 },{ 0x1117c1, 0x0 },{ 0x2117c1, 0x0 },{ 0x118c1, 0x0 },{ 0x1118c1, 0x0 },{ 0x2118c1, 0x0 },{ 0x120c1, 0x0 },{ 0x1120c1, 0x0 },{ 0x2120c1, 0x0 },{ 0x121c1, 0x0 },{ 0x1121c1, 0x0 },{ 0x2121c1, 0x0 },{ 0x122c1, 0x0 },{ 0x1122c1, 0x0 },{ 0x2122c1, 0x0 },{ 0x123c1, 0x0 },{ 0x1123c1, 0x0 },{ 0x2123c1, 0x0 },{ 0x124c1, 0x0 },{ 0x1124c1, 0x0 },{ 0x2124c1, 0x0 },{ 0x125c1, 0x0 },{ 0x1125c1, 0x0 },{ 0x2125c1, 0x0 },{ 0x126c1, 0x0 },{ 0x1126c1, 0x0 },{ 0x2126c1, 0x0 },{ 0x127c1, 0x0 },{ 0x1127c1, 0x0 },{ 0x2127c1, 0x0 },{ 0x128c1, 0x0 },{ 0x1128c1, 0x0 },{ 0x2128c1, 0x0 },{ 0x130c1, 0x0 },{ 0x1130c1, 0x0 },{ 0x2130c1, 0x0 },{ 0x131c1, 0x0 },{ 0x1131c1, 0x0 },{ 0x2131c1, 0x0 },{ 0x132c1, 0x0 },{ 0x1132c1, 0x0 },{ 0x2132c1, 0x0 },{ 0x133c1, 0x0 },{ 0x1133c1, 0x0 },{ 0x2133c1, 0x0 },{ 0x134c1, 0x0 },{ 0x1134c1, 0x0 },{ 0x2134c1, 0x0 },{ 0x135c1, 0x0 },{ 0x1135c1, 0x0 },{ 0x2135c1, 0x0 },{ 0x136c1, 0x0 },{ 0x1136c1, 0x0 },{ 0x2136c1, 0x0 },{ 0x137c1, 0x0 },{ 0x1137c1, 0x0 },{ 0x2137c1, 0x0 },{ 0x138c1, 0x0 },{ 0x1138c1, 0x0 },{ 0x2138c1, 0x0 },{ 0x10020, 0x0 },{ 0x110020, 0x0 },{ 0x210020, 0x0 },{ 0x11020, 0x0 },{ 0x111020, 0x0 },{ 0x211020, 0x0 },{ 0x12020, 0x0 },{ 0x112020, 0x0 },{ 0x212020, 0x0 },{ 0x13020, 0x0 },{ 0x113020, 0x0 },{ 0x213020, 0x0 },{ 0x20072, 0x0 },{ 0x20073, 0x0 },{ 0x20074, 0x0 },{ 0x100aa, 0x0 },{ 0x110aa, 0x0 },{ 0x120aa, 0x0 },{ 0x130aa, 0x0 },{ 0x20010, 0x0 },{ 0x120010, 0x0 },{ 0x220010, 0x0 },{ 0x20011, 0x0 },{ 0x120011, 0x0 },{ 0x220011, 0x0 },{ 0x100ae, 0x0 },{ 0x1100ae, 0x0 },{ 0x2100ae, 0x0 },{ 0x100af, 0x0 },{ 0x1100af, 0x0 },{ 0x2100af, 0x0 },{ 0x110ae, 0x0 },{ 0x1110ae, 0x0 },{ 0x2110ae, 0x0 },{ 0x110af, 0x0 },{ 0x1110af, 0x0 },{ 0x2110af, 0x0 },{ 0x120ae, 0x0 },{ 0x1120ae, 0x0 },{ 0x2120ae, 0x0 },{ 0x120af, 0x0 },{ 0x1120af, 0x0 },{ 0x2120af, 0x0 },{ 0x130ae, 0x0 },{ 0x1130ae, 0x0 },{ 0x2130ae, 0x0 },{ 0x130af, 0x0 },{ 0x1130af, 0x0 },{ 0x2130af, 0x0 },{ 0x20020, 0x0 },{ 0x120020, 0x0 },{ 0x220020, 0x0 },{ 0x100a0, 0x0 },{ 0x100a1, 0x0 },{ 0x100a2, 0x0 },{ 0x100a3, 0x0 },{ 0x100a4, 0x0 },{ 0x100a5, 0x0 },{ 0x100a6, 0x0 },{ 0x100a7, 0x0 },{ 0x110a0, 0x0 },{ 0x110a1, 0x0 },{ 0x110a2, 0x0 },{ 0x110a3, 0x0 },{ 0x110a4, 0x0 },{ 0x110a5, 0x0 },{ 0x110a6, 0x0 },{ 0x110a7, 0x0 },{ 0x120a0, 0x0 },{ 0x120a1, 0x0 },{ 0x120a2, 0x0 },{ 0x120a3, 0x0 },{ 0x120a4, 0x0 },{ 0x120a5, 0x0 },{ 0x120a6, 0x0 },{ 0x120a7, 0x0 },{ 0x130a0, 0x0 },{ 0x130a1, 0x0 },{ 0x130a2, 0x0 },{ 0x130a3, 0x0 },{ 0x130a4, 0x0 },{ 0x130a5, 0x0 },{ 0x130a6, 0x0 },{ 0x130a7, 0x0 },{ 0x2007c, 0x0 },{ 0x12007c, 0x0 },{ 0x22007c, 0x0 },{ 0x2007d, 0x0 },{ 0x12007d, 0x0 },{ 0x22007d, 0x0 },{ 0x400fd, 0x0 },{ 0x400c0, 0x0 },{ 0x90201, 0x0 },{ 0x190201, 0x0 },{ 0x290201, 0x0 },{ 0x90202, 0x0 },{ 0x190202, 0x0 },{ 0x290202, 0x0 },{ 0x90203, 0x0 },{ 0x190203, 0x0 },{ 0x290203, 0x0 },{ 0x90204, 0x0 },{ 0x190204, 0x0 },{ 0x290204, 0x0 },{ 0x90205, 0x0 },{ 0x190205, 0x0 },{ 0x290205, 0x0 },{ 0x90206, 0x0 },{ 0x190206, 0x0 },{ 0x290206, 0x0 },{ 0x90207, 0x0 },{ 0x190207, 0x0 },{ 0x290207, 0x0 },{ 0x90208, 0x0 },{ 0x190208, 0x0 },{ 0x290208, 0x0 },{ 0x10062, 0x0 },{ 0x10162, 0x0 },{ 0x10262, 0x0 },{ 0x10362, 0x0 },{ 0x10462, 0x0 },{ 0x10562, 0x0 },{ 0x10662, 0x0 },{ 0x10762, 0x0 },{ 0x10862, 0x0 },{ 0x11062, 0x0 },{ 0x11162, 0x0 },{ 0x11262, 0x0 },{ 0x11362, 0x0 },{ 0x11462, 0x0 },{ 0x11562, 0x0 },{ 0x11662, 0x0 },{ 0x11762, 0x0 },{ 0x11862, 0x0 },{ 0x12062, 0x0 },{ 0x12162, 0x0 },{ 0x12262, 0x0 },{ 0x12362, 0x0 },{ 0x12462, 0x0 },{ 0x12562, 0x0 },{ 0x12662, 0x0 },{ 0x12762, 0x0 },{ 0x12862, 0x0 },{ 0x13062, 0x0 },{ 0x13162, 0x0 },{ 0x13262, 0x0 },{ 0x13362, 0x0 },{ 0x13462, 0x0 },{ 0x13562, 0x0 },{ 0x13662, 0x0 },{ 0x13762, 0x0 },{ 0x13862, 0x0 },{ 0x20077, 0x0 },{ 0x10001, 0x0 },{ 0x11001, 0x0 },{ 0x12001, 0x0 },{ 0x13001, 0x0 },{ 0x10040, 0x0 },{ 0x10140, 0x0 },{ 0x10240, 0x0 },{ 0x10340, 0x0 },{ 0x10440, 0x0 },{ 0x10540, 0x0 },{ 0x10640, 0x0 },{ 0x10740, 0x0 },{ 0x10840, 0x0 },{ 0x10030, 0x0 },{ 0x10130, 0x0 },{ 0x10230, 0x0 },{ 0x10330, 0x0 },{ 0x10430, 0x0 },{ 0x10530, 0x0 },{ 0x10630, 0x0 },{ 0x10730, 0x0 },{ 0x10830, 0x0 },{ 0x11040, 0x0 },{ 0x11140, 0x0 },{ 0x11240, 0x0 },{ 0x11340, 0x0 },{ 0x11440, 0x0 },{ 0x11540, 0x0 },{ 0x11640, 0x0 },{ 0x11740, 0x0 },{ 0x11840, 0x0 },{ 0x11030, 0x0 },{ 0x11130, 0x0 },{ 0x11230, 0x0 },{ 0x11330, 0x0 },{ 0x11430, 0x0 },{ 0x11530, 0x0 },{ 0x11630, 0x0 },{ 0x11730, 0x0 },{ 0x11830, 0x0 },{ 0x12040, 0x0 },{ 0x12140, 0x0 },{ 0x12240, 0x0 },{ 0x12340, 0x0 },{ 0x12440, 0x0 },{ 0x12540, 0x0 },{ 0x12640, 0x0 },{ 0x12740, 0x0 },{ 0x12840, 0x0 },{ 0x12030, 0x0 },{ 0x12130, 0x0 },{ 0x12230, 0x0 },{ 0x12330, 0x0 },{ 0x12430, 0x0 },{ 0x12530, 0x0 },{ 0x12630, 0x0 },{ 0x12730, 0x0 },{ 0x12830, 0x0 },{ 0x13040, 0x0 },{ 0x13140, 0x0 },{ 0x13240, 0x0 },{ 0x13340, 0x0 },{ 0x13440, 0x0 },{ 0x13540, 0x0 },{ 0x13640, 0x0 },{ 0x13740, 0x0 },{ 0x13840, 0x0 },{ 0x13030, 0x0 },{ 0x13130, 0x0 },{ 0x13230, 0x0 },{ 0x13330, 0x0 },{ 0x13430, 0x0 },{ 0x13530, 0x0 },{ 0x13630, 0x0 },{ 0x13730, 0x0 },{ 0x13830, 0x0 },+};
+/* P0 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_cfg[] = {
{0xd0000, 0x0},{0x54003, 0xbb8},{0x54004, 0x2},{0x54005, 0x2228},{0x54006, 0x11},{0x54008, 0x131f},{0x54009, 0xc8},{0x5400b, 0x2},{0x5400d, 0x100},{0x54012, 0x110},{0x54019, 0x2dd4},{0x5401a, 0x31},{0x5401b, 0x4d66},{0x5401c, 0x4d00},{0x5401e, 0x16},{0x5401f, 0x2dd4},{0x54020, 0x31},{0x54021, 0x4d66},{0x54022, 0x4d00},{0x54024, 0x16},{0x5402b, 0x1000},{0x5402c, 0x1},{0x54032, 0xd400},{0x54033, 0x312d},{0x54034, 0x6600},{0x54035, 0x4d},{0x54036, 0x4d},{0x54037, 0x1600},{0x54038, 0xd400},{0x54039, 0x312d},{0x5403a, 0x6600},{0x5403b, 0x4d},{0x5403c, 0x4d},{0x5403d, 0x1600},{0xd0000, 0x1},+};
+/* P1 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp1_cfg[] = {
{0xd0000, 0x0},{0x54002, 0x101},{0x54003, 0x190},{0x54004, 0x2},{0x54005, 0x2228},{0x54006, 0x11},{0x54008, 0x121f},{0x54009, 0xc8},{0x5400b, 0x2},{0x5400d, 0x100},{0x54012, 0x110},{0x54019, 0x84},{0x5401a, 0x31},{0x5401b, 0x4d66},{0x5401c, 0x4d00},{0x5401e, 0x16},{0x5401f, 0x84},{0x54020, 0x31},{0x54021, 0x4d66},{0x54022, 0x4d00},{0x54024, 0x16},{0x5402b, 0x1000},{0x5402c, 0x1},{0x54032, 0x8400},{0x54033, 0x3100},{0x54034, 0x6600},{0x54035, 0x4d},{0x54036, 0x4d},{0x54037, 0x1600},{0x54038, 0x8400},{0x54039, 0x3100},{0x5403a, 0x6600},{0x5403b, 0x4d},{0x5403c, 0x4d},{0x5403d, 0x1600},{0xd0000, 0x1},+};
+/* P2 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp2_cfg[] = {
{0xd0000, 0x0},{0x54002, 0x102},{0x54003, 0x64},{0x54004, 0x2},{0x54005, 0x2228},{0x54006, 0x11},{0x54008, 0x121f},{0x54009, 0xc8},{0x5400b, 0x2},{0x5400d, 0x100},{0x54012, 0x110},{0x54019, 0x84},{0x5401a, 0x31},{0x5401b, 0x4d66},{0x5401c, 0x4d00},{0x5401e, 0x16},{0x5401f, 0x84},{0x54020, 0x31},{0x54021, 0x4d66},{0x54022, 0x4d00},{0x54024, 0x16},{0x5402b, 0x1000},{0x5402c, 0x1},{0x54032, 0x8400},{0x54033, 0x3100},{0x54034, 0x6600},{0x54035, 0x4d},{0x54036, 0x4d},{0x54037, 0x1600},{0x54038, 0x8400},{0x54039, 0x3100},{0x5403a, 0x6600},{0x5403b, 0x4d},{0x5403c, 0x4d},{0x5403d, 0x1600},{0xd0000, 0x1},+};
+/* P0 2D message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
{0xd0000, 0x0},{0x54003, 0xbb8},{0x54004, 0x2},{0x54005, 0x2228},{0x54006, 0x11},{0x54008, 0x61},{0x54009, 0xc8},{0x5400b, 0x2},{0x5400f, 0x100},{0x54010, 0x1f7f},{0x54012, 0x110},{0x54019, 0x2dd4},{0x5401a, 0x31},{0x5401b, 0x4d66},{0x5401c, 0x4d00},{0x5401e, 0x16},{0x5401f, 0x2dd4},{0x54020, 0x31},{0x54021, 0x4d66},{0x54022, 0x4d00},{0x54024, 0x16},{0x5402b, 0x1000},{0x5402c, 0x1},{0x54032, 0xd400},{0x54033, 0x312d},{0x54034, 0x6600},{0x54035, 0x4d},{0x54036, 0x4d},{0x54037, 0x1600},{0x54038, 0xd400},{0x54039, 0x312d},{0x5403a, 0x6600},{0x5403b, 0x4d},{0x5403c, 0x4d},{0x5403d, 0x1600},{ 0xd0000, 0x1 },+};
+/* DRAM PHY init engine image */ +struct dram_cfg_param ddr_phy_pie[] = {
{0xd0000, 0x0},{0x90000, 0x10},{0x90001, 0x400},{0x90002, 0x10e},{0x90003, 0x0},{0x90004, 0x0},{0x90005, 0x8},{0x90029, 0xb},{0x9002a, 0x480},{0x9002b, 0x109},{0x9002c, 0x8},{0x9002d, 0x448},{0x9002e, 0x139},{0x9002f, 0x8},{0x90030, 0x478},{0x90031, 0x109},{0x90032, 0x0},{0x90033, 0xe8},{0x90034, 0x109},{0x90035, 0x2},{0x90036, 0x10},{0x90037, 0x139},{0x90038, 0xf},{0x90039, 0x7c0},{0x9003a, 0x139},{0x9003b, 0x44},{0x9003c, 0x630},{0x9003d, 0x159},{0x9003e, 0x14f},{0x9003f, 0x630},{0x90040, 0x159},{0x90041, 0x47},{0x90042, 0x630},{0x90043, 0x149},{0x90044, 0x4f},{0x90045, 0x630},{0x90046, 0x179},{0x90047, 0x8},{0x90048, 0xe0},{0x90049, 0x109},{0x9004a, 0x0},{0x9004b, 0x7c8},{0x9004c, 0x109},{0x9004d, 0x0},{0x9004e, 0x1},{0x9004f, 0x8},{0x90050, 0x0},{0x90051, 0x45a},{0x90052, 0x9},{0x90053, 0x0},{0x90054, 0x448},{0x90055, 0x109},{0x90056, 0x40},{0x90057, 0x630},{0x90058, 0x179},{0x90059, 0x1},{0x9005a, 0x618},{0x9005b, 0x109},{0x9005c, 0x40c0},{0x9005d, 0x630},{0x9005e, 0x149},{0x9005f, 0x8},{0x90060, 0x4},{0x90061, 0x48},{0x90062, 0x4040},{0x90063, 0x630},{0x90064, 0x149},{0x90065, 0x0},{0x90066, 0x4},{0x90067, 0x48},{0x90068, 0x40},{0x90069, 0x630},{0x9006a, 0x149},{0x9006b, 0x10},{0x9006c, 0x4},{0x9006d, 0x18},{0x9006e, 0x0},{0x9006f, 0x4},{0x90070, 0x78},{0x90071, 0x549},{0x90072, 0x630},{0x90073, 0x159},{0x90074, 0xd49},{0x90075, 0x630},{0x90076, 0x159},{0x90077, 0x94a},{0x90078, 0x630},{0x90079, 0x159},{0x9007a, 0x441},{0x9007b, 0x630},{0x9007c, 0x149},{0x9007d, 0x42},{0x9007e, 0x630},{0x9007f, 0x149},{0x90080, 0x1},{0x90081, 0x630},{0x90082, 0x149},{0x90083, 0x0},{0x90084, 0xe0},{0x90085, 0x109},{0x90086, 0xa},{0x90087, 0x10},{0x90088, 0x109},{0x90089, 0x9},{0x9008a, 0x3c0},{0x9008b, 0x149},{0x9008c, 0x9},{0x9008d, 0x3c0},{0x9008e, 0x159},{0x9008f, 0x18},{0x90090, 0x10},{0x90091, 0x109},{0x90092, 0x0},{0x90093, 0x3c0},{0x90094, 0x109},{0x90095, 0x18},{0x90096, 0x4},{0x90097, 0x48},{0x90098, 0x18},{0x90099, 0x4},{0x9009a, 0x58},{0x9009b, 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0x5d},{0x2000c, 0xbb},{0x2000d, 0x753},{0x2000e, 0x2c},{0x12000b, 0xc},{0x12000c, 0x19},{0x12000d, 0xfa},{0x12000e, 0x10},{0x22000b, 0x3},{0x22000c, 0x6},{0x22000d, 0x3e},{0x22000e, 0x10},{0x9000c, 0x0},{0x9000d, 0x173},{0x9000e, 0x60},{0x9000f, 0x6110},{0x90010, 0x2152},{0x90011, 0xdfbd},{0x90012, 0x60},{0x90013, 0x6152},{0x20010, 0x5a},{0x20011, 0x3},{0x120010, 0x5a},{0x120011, 0x3},{0x220010, 0x5a},{0x220011, 0x3},{0x40080, 0xe0},{0x40081, 0x12},{0x40082, 0xe0},{0x40083, 0x12},{0x40084, 0xe0},{0x40085, 0x12},{0x140080, 0xe0},{0x140081, 0x12},{0x140082, 0xe0},{0x140083, 0x12},{0x140084, 0xe0},{0x140085, 0x12},{0x240080, 0xe0},{0x240081, 0x12},{0x240082, 0xe0},{0x240083, 0x12},{0x240084, 0xe0},{0x240085, 0x12},{0x400fd, 0xf},{0x10011, 0x1},{0x10012, 0x1},{0x10013, 0x180},{0x10018, 0x1},{0x10002, 0x6209},{0x100b2, 0x1},{0x101b4, 0x1},{0x102b4, 0x1},{0x103b4, 0x1},{0x104b4, 0x1},{0x105b4, 0x1},{0x106b4, 0x1},{0x107b4, 0x1},{0x108b4, 0x1},{0x11011, 0x1},{0x11012, 0x1},{0x11013, 0x180},{0x11018, 0x1},{0x11002, 0x6209},{0x110b2, 0x1},{0x111b4, 0x1},{0x112b4, 0x1},{0x113b4, 0x1},{0x114b4, 0x1},{0x115b4, 0x1},{0x116b4, 0x1},{0x117b4, 0x1},{0x118b4, 0x1},{0x12011, 0x1},{0x12012, 0x1},{0x12013, 0x180},{0x12018, 0x1},{0x12002, 0x6209},{0x120b2, 0x1},{0x121b4, 0x1},{0x122b4, 0x1},{0x123b4, 0x1},{0x124b4, 0x1},{0x125b4, 0x1},{0x126b4, 0x1},{0x127b4, 0x1},{0x128b4, 0x1},{0x13011, 0x1},{0x13012, 0x1},{0x13013, 0x180},{0x13018, 0x1},{0x13002, 0x6209},{0x130b2, 0x1},{0x131b4, 0x1},{0x132b4, 0x1},{0x133b4, 0x1},{0x134b4, 0x1},{0x135b4, 0x1},{0x136b4, 0x1},{0x137b4, 0x1},{0x138b4, 0x1},{0x2003a, 0x2},{0xc0080, 0x2},{0xd0000, 0x1}+};
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
{/* P0 3000mts 1D */.drate = 3000,.fw_type = FW_1D_IMAGE,.fsp_cfg = ddr_fsp0_cfg,.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),},{/* P1 400mts 1D */.drate = 400,.fw_type = FW_1D_IMAGE,.fsp_cfg = ddr_fsp1_cfg,.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),},{/* P2 100mts 1D */.drate = 100,.fw_type = FW_1D_IMAGE,.fsp_cfg = ddr_fsp2_cfg,.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),},{/* P0 3000mts 2D */.drate = 3000,.fw_type = FW_2D_IMAGE,.fsp_cfg = ddr_fsp0_2d_cfg,.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),},+};
+/* ddr timing config params */ +struct dram_timing_info dram_timing = {
.ddrc_cfg = ddr_ddrc_cfg,.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),.ddrphy_cfg = ddr_ddrphy_cfg,.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),.fsp_msg = ddr_dram_fsp_msg,.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),.ddrphy_trained_csr = ddr_ddrphy_trained_csr,.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),.ddrphy_pie = ddr_phy_pie,.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),.fsp_table = { 3000, 400, 100, },+}; diff --git a/board/toradex/verdin-imx8mm/spl.c b/board/toradex/verdin-imx8mm/spl.c new file mode 100644 index 0000000000..a5dc540820 --- /dev/null +++ b/board/toradex/verdin-imx8mm/spl.c @@ -0,0 +1,180 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Copyright 2020 Toradex
- */
+#include <common.h> +#include <asm/arch/clock.h> +#include <asm/arch/ddr.h> +#include <asm/arch/imx8mm_pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/io.h> +#include <asm/mach-imx/boot_mode.h> +#include <asm/mach-imx/iomux-v3.h> +#include <cpu_func.h> +#include <dm/device.h> +#include <dm/device-internal.h> +#include <dm/uclass.h> +#include <dm/uclass-internal.h> +#include <hang.h> +#include <power/bd71837.h> +#include <power/pmic.h> +#include <spl.h>
+DECLARE_GLOBAL_DATA_PTR;
+int spl_board_boot_device(enum boot_device boot_dev_spl) +{
switch (boot_dev_spl) {case MMC1_BOOT:return BOOT_DEVICE_MMC1;case SD2_BOOT:case MMC2_BOOT:return BOOT_DEVICE_MMC2;case SD3_BOOT:case MMC3_BOOT:return BOOT_DEVICE_MMC1;case USB_BOOT:return BOOT_DEVICE_BOARD;default:return BOOT_DEVICE_NONE;}+}
+void spl_dram_init(void) +{
ddr_init(&dram_timing);+}
+void spl_board_init(void) +{
/* Serial download mode */if (is_usb_boot()) {puts("Back to ROM, SDP\n");restore_boot_params();}puts("Normal Boot\n");+}
+#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{
/* Just empty function now - can't decide what to choose */debug("%s: %s\n", __func__, name);return 0;+} +#endif
+#define UART_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PE | PAD_CTL_DSE4) +#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
+/* Verdin UART_3, Console/Debug UART */ +static iomux_v3_cfg_t const uart_pads[] = {
IMX8MM_PAD_SAI2_RXFS_UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),IMX8MM_PAD_SAI2_RXC_UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),+};
+static iomux_v3_cfg_t const wdog_pads[] = {
IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),+};
+int board_early_init_f(void) +{
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));set_wdog_reset(wdog);imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));return 0;+}
+int power_init_board(void) +{
struct udevice *dev;int ret;ret = pmic_get("pmic@4b", &dev);if (ret == -ENODEV) {puts("No pmic\n");return 0;}if (ret != 0)return ret;/* decrease RESET key long push time from the default 10s to 10ms */pmic_reg_write(dev, BD718XX_PWRONCONFIG1, 0x0);/* unlock the PMIC regs */pmic_reg_write(dev, BD718XX_REGLOCK, 0x1);/* increase VDD_SOC to typical value 0.85v before first DRAM access */pmic_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0x0f);/* increase VDD_DRAM to 0.975v for 3Ghz DDR */pmic_reg_write(dev, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83);+#ifndef CONFIG_IMX8M_LPDDR4
/* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */pmic_reg_write(dev, BD718XX_4TH_NODVS_BUCK_VOLT, 0x28);+#endif
/* lock the PMIC regs */pmic_reg_write(dev, BD718XX_REGLOCK, 0x11);return 0;+}
+void board_init_f(ulong dummy) +{
struct udevice *dev;int ret;arch_cpu_init();init_uart_clk(0);board_early_init_f();timer_init();preloader_console_init();/* Clear the BSS. */memset(__bss_start, 0, __bss_end - __bss_start);ret = spl_early_init();if (ret) {debug("spl_early_init() failed: %d\n", ret);hang();}ret = uclass_get_device_by_name(UCLASS_CLK,"clock-controller@30380000",&dev);if (ret < 0) {printf("Failed to find clock node. Check device tree\n");hang();}enable_tzc380();power_init_board();/* DDR initialization */spl_dram_init();board_init_r(NULL, 0);+}
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{
puts("resetting ...\n");reset_cpu(WDOG1_BASE_ADDR);return 0;+} diff --git a/board/toradex/verdin-imx8mm/verdin-imx8mm.c b/board/toradex/verdin-imx8mm/verdin-imx8mm.c new file mode 100644 index 0000000000..16b9fa1ec1 --- /dev/null +++ b/board/toradex/verdin-imx8mm/verdin-imx8mm.c @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Copyright 2020 Toradex
- */
+#include <common.h> +#include <asm/arch/clock.h> +#include <asm/io.h> +#include <miiphy.h> +#include <netdev.h>
+DECLARE_GLOBAL_DATA_PTR;
+int dram_init(void) +{
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);return 0;+}
+#if IS_ENABLED(CONFIG_FEC_MXC) +static int setup_fec(void) +{
struct iomuxc_gpr_base_regs *gpr =(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;/* Use 125M anatop REF_CLK1 for ENET1, not from external */clrsetbits_le32(&gpr->gpr[1], 0x2000, 0);return 0;+}
+int board_phy_config(struct phy_device *phydev) +{
/* enable rgmii rxc skew and phy mode select to RGMII copper */phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);if (phydev->drv->config)phydev->drv->config(phydev);return 0;+} +#endif
+int board_init(void) +{
if (IS_ENABLED(CONFIG_FEC_MXC))setup_fec();return 0;+}
+int board_mmc_get_env_dev(int devno) +{
return devno;+}
+int board_late_init(void) +{
return 0;+}
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, bd_t *bd) +{
return 0;+} +#endif diff --git a/configs/verdin-imx8mm_defconfig b/configs/verdin-imx8mm_defconfig new file mode 100644 index 0000000000..3a7aa8de82 --- /dev/null +++ b/configs/verdin-imx8mm_defconfig @@ -0,0 +1,98 @@ +CONFIG_ARM=y +CONFIG_SPL_SYS_ICACHE_OFF=y +CONFIG_SPL_SYS_DCACHE_OFF=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x10000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xFFFFDE00 +CONFIG_DM_GPIO=y +CONFIG_TARGET_VERDIN_IMX8MM=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_SPL_TEXT_BASE=0x7E1000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/verdin-imx8mm/imximage.cfg" +CONFIG_DEFAULT_FDT_FILE="fsl-imx8mm-verdin-dev.dtb" +# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_LOG=y +CONFIG_VERSION_VARIABLE=y +CONFIG_BOARD_LATE_INIT=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SYS_PROMPT="Verdin iMX8MM # " +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_ASKENV=y +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_UUID=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT4_WRITE=y +# CONFIG_ISO_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx8mm-verdin" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_IP_DEFRAG=y +CONFIG_TFTP_BLOCKSIZE=4096 +CONFIG_SPL_DM=y +CONFIG_SPL_CLK_COMPOSITE_CCF=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMX8MM=y +CONFIG_CLK_IMX8MM=y +CONFIG_MXC_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_ESDHC_IMX=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_PMIC=y +CONFIG_SPL_DM_PMIC_BD71837=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y diff --git a/include/configs/verdin-imx8mm.h b/include/configs/verdin-imx8mm.h new file mode 100644 index 0000000000..dc0a2efec6 --- /dev/null +++ b/include/configs/verdin-imx8mm.h @@ -0,0 +1,128 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*
- Copyright 2020 Toradex
- */
+#ifndef __VERDIN_IMX8MM_H +#define __VERDIN_IMX8MM_H
+#include <asm/arch/imx-regs.h> +#include <linux/sizes.h>
+#ifdef CONFIG_SECURE_BOOT +#define CONFIG_CSF_SIZE SZ_8K +#endif
+#define CONFIG_SPL_MAX_SIZE (148 * 1024) +#define CONFIG_SYS_MONITOR_LEN SZ_512K +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#define CONFIG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)+#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_STACK 0x920000 +#define CONFIG_SPL_BSS_START_ADDR 0x910000 +#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 +#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */
+/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ +#define CONFIG_MALLOC_F_ADDR 0x930000 +/* For RAW image gives a error info not panic */ +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE +#endif
+#define MEM_LAYOUT_ENV_SETTINGS \
"fdt_addr_r=0x44000000\0" \"kernel_addr_r=0x42000000\0" \"ramdisk_addr_r=0x46400000\0" \"scriptaddr=0x46000000\0"+#define CONFIG_LOADADDR 0x40480000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+/* Enable Distro Boot */ +#ifndef CONFIG_SPL_BUILD +#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 1) \func(MMC, mmc, 0) \func(DHCP, dhcp, na)+#include <config_distro_bootcmd.h> +#undef CONFIG_ISO_PARTITION +#else +#define BOOTENV +#endif
+/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \
BOOTENV \MEM_LAYOUT_ENV_SETTINGS \"bootcmd_mfg=fastboot 0\0" \"console=ttymxc0\0" \"fdt_addr=0x43000000\0" \"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \"initrd_addr=0x43800000\0" \"initrd_high=0xffffffffffffffff\0" \"kernel_image=Image\0" \"setup=setenv setupargs console=${console},${baudrate} " \"console=tty1 consoleblank=0 earlycon\0" \"update_uboot=askenv confirm Did you load flash.bin (y/N)?; " \"if test \"$confirm\" = \"y\"; then " \"setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \"${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x2 " \"${blkcnt}; fi\0"+#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 +#define CONFIG_SYS_INIT_RAM_SIZE SZ_2M +#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)+#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)+#define CONFIG_ENV_OVERWRITE +#if defined(CONFIG_ENV_IS_IN_MMC) +/* Environment in eMMC, before config block at the end of 1st "boot sector" */ +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 eMMC */ +#define CONFIG_SYS_MMC_ENV_PART 1 +#endif
+/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN SZ_32M +#define CONFIG_SYS_SDRAM_BASE 0x40000000
+/* SDRAM configuration */ +#define PHYS_SDRAM 0x40000000 +#define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */
+#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
(PHYS_SDRAM_SIZE >> 1))+/* UART */ +#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR
+/* Monitor Command Prompt */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_CBSIZE SZ_2K +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)+/* USDHC */ +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 +#define CONFIG_SYS_I2C_SPEED 100000
+/* ENET */ +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_FEC_MXC_PHYADDR 7 +#define FEC_QUIRK_ENET_MAC +#define IMX_FEC_BASE 0x30BE0000
+#endif /*_VERDIN_IMX8MM_H */
-- 2.24.1