Hi all,
Am Freitag, 28. Januar 2022, 14:47:13 CEST schrieb Alexandre Ghiti:
The following description is copied from the equivalent patch for the Linux Kernel proposed by Aurelien Jarno:
From version 2.38, binutils default to ISA spec version 20191213. This means that the csr read/write (csrr*/csrw*) instructions and fence.i instruction has separated from the `I` extension, become two standalone extensions: Zicsr and Zifencei. As the kernel uses those instruction, this causes the following build failure:
arch/riscv/cpu/mtrap.S: Assembler messages: arch/riscv/cpu/mtrap.S:65: Error: unrecognized opcode `csrr a0,scause' arch/riscv/cpu/mtrap.S:66: Error: unrecognized opcode `csrr a1,sepc' arch/riscv/cpu/mtrap.S:67: Error: unrecognized opcode `csrr a2,stval' arch/riscv/cpu/mtrap.S:70: Error: unrecognized opcode `csrw sepc,a0'
Signed-off-by: Alexandre Ghiti alexandre.ghiti@canonical.com
Heiko wrote:
Is there progress in getting this patch applied to u-boot in some way? Also it looks like there was another patch with similar content submitted recently [0].
In any case:
On a D1-Nezha it fixes the build (and boot) Tested-by: Heiko Stuebner heiko@sntech.de
Fixes the boot with u-boot in Buildroot:
[0] https://lore.kernel.org/all/PH7PR14MB5594FD11D1BE74284F554BEBCED49@PH7PR14MB... [1] https://github.com/skiffos/u-boot/commit/3bb93519563146419aa06e8d21394089163...
This is for a few Risc-v boards based on D1.
Tested-by: Christian Stewart christian@paral.in
Thanks & best, Christian Stewart