Re: [U-Boot] [PATCH 2/3] dnet: driver for Dave DNET ethernet controller

Hi Ilya,

Ilya Yanok wrote:

Driver for Dave DNET ethernet controller (used on Dave/DENX QongEVB-LITE board).

Signed-off-by: Ilya Yanok yanok@emcraft.com

drivers/net/Makefile | 1 + drivers/net/dnet.c | 405 ++++++++++++++++++++++++++++++++++++++++++++++++++ drivers/net/dnet.h | 169 +++++++++++++++++++++ 3 files changed, 575 insertions(+), 0 deletions(-) create mode 100644 drivers/net/dnet.c create mode 100644 drivers/net/dnet.h

You need to add your initialize() function to include/netdev.h

diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 631336a..a1084a6 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -69,6 +69,7 @@ COBJS-$(CONFIG_VSC7385_ENET) += vsc7385.o COBJS-$(CONFIG_XILINX_EMAC) += xilinx_emac.o COBJS-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o COBJS-$(CONFIG_SH_ETHER) += sh_eth.o +COBJS-$(CONFIG_DRIVER_DNET) += dnet.o

In alphabetical order, please. (ignore the other transgressions)

COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/net/dnet.c b/drivers/net/dnet.c new file mode 100644 index 0000000..4513707 --- /dev/null +++ b/drivers/net/dnet.c @@ -0,0 +1,405 @@ +/*

• • Dave Ethernet Controller driver
• • Copyright (C) 2008 Dave S.r.l. <www.dave.eu>
• • This program is free software; you can redistribute it and/or modify
• • it under the terms of the GNU General Public License version 2 as
• • published by the Free Software Foundation.
• */

+#include <common.h>

+#if defined(CONFIG_DRIVER_DNET) \

• && (defined(CONFIG_CMD_NET) || defined(CONFIG_CMD_MII))

Not needed, this is taken care of in the Makefile

+#define CFG_DNET_AUTONEG_TIMEOUT 5000000

+#include <net.h> +#include <malloc.h> +#include <linux/mii.h>

+#include <miiphy.h> +#include <asm/io.h>

+#include "dnet.h"

+struct dnet_device {

• void *regs;

Surely you know enough about this to define its type

• const struct device *dev;
• struct eth_device netdev;
• unsigned short phy_addr;

+};

+#define to_dnet(_nd) container_of(_nd, struct dnet_device, netdev)

+/* function for reading internal MAC register */ +u16 dnet_readw_mac(struct dnet_device *dnet, u16 reg) +{

• u16 data_read;
• /* issue a read */
• dnet_writel(dnet, reg, MACREG_ADDR);
• /* since a read/write op to the MAC is very slow,

• * we must wait before reading the data */
  

• udelay(1);
• /* read data read from the MAC register */
• data_read = dnet_readl(dnet, MACREG_DATA);
• /* all done */
• return(data_read);

+}

+/* function for writing internal MAC register */ +void dnet_writew_mac(struct dnet_device *dnet, u16 reg, u16 val) +{

• /* load data to write */
• dnet_writel(dnet, val, MACREG_DATA);
• /* issue a write */
• dnet_writel(dnet, reg | DNET_INTERNAL_WRITE, MACREG_ADDR);
• /* since a read/write op to the MAC is very slow,

• * we must wait before exiting */
  

• udelay(1);
• /* all done */
• return;

Not necessary to return

+}

+static void dnet_mdio_write(struct dnet_device *dnet, u8 reg, u16 value) +{

• u16 tmp;
• debug(DRIVERNAME "dnet_mdio_write %02x:%02x <- %04x\n",

• 	dnet->phy_addr, reg, value);
  

• while (!(dnet_readw_mac(dnet, DNET_INTERNAL_GMII_MNG_CTL_REG) &

• 		DNET_INTERNAL_GMII_MNG_CMD_FIN));
  

• /* prepare for a write operation */
• tmp = (1 << 13);
• /* only 5 bits allowed for register offset */
• reg &= 0x1f;
• /* prepare reg_value for a write */
• tmp |= (dnet->phy_addr << 8);
• tmp |= reg;
• /* write data to write first */
• dnet_writew_mac(dnet, DNET_INTERNAL_GMII_MNG_DAT_REG, value);
• /* write control word */
• dnet_writew_mac(dnet, DNET_INTERNAL_GMII_MNG_CTL_REG, tmp);
• while (!(dnet_readw_mac(dnet, DNET_INTERNAL_GMII_MNG_CTL_REG) &

• 		DNET_INTERNAL_GMII_MNG_CMD_FIN));
  

+}

+static u16 dnet_mdio_read(struct dnet_device *dnet, u8 reg) +{

• u16 value;
• while (!(dnet_readw_mac(dnet, DNET_INTERNAL_GMII_MNG_CTL_REG) &

• 		DNET_INTERNAL_GMII_MNG_CMD_FIN));
  

• /* only 5 bits allowed for register offset*/
• reg &= 0x1f;
• /* prepare reg_value for a read */
• value = (dnet->phy_addr << 8);
• value |= reg;
• /* write control word */
• dnet_writew_mac(dnet, DNET_INTERNAL_GMII_MNG_CTL_REG, value);
• /* wait for end of transfer */
• while (!(dnet_readw_mac(dnet, DNET_INTERNAL_GMII_MNG_CTL_REG) &

• 		DNET_INTERNAL_GMII_MNG_CMD_FIN));
  

• value = dnet_readw_mac(dnet, DNET_INTERNAL_GMII_MNG_DAT_REG);
• debug(DRIVERNAME "dnet_mdio_read %02x:%02x <- %04x\n",

• dnet->phy_addr, reg, value);
  

• return value;

+}

+#if defined(CONFIG_CMD_NET)

Not necessary

+static int dnet_send(struct eth_device *netdev, volatile void *packet,

•      int length)
  

+{

• struct dnet_device *dnet = to_dnet(netdev);
• int i, len, wrsz;
• unsigned int * bufp;
• unsigned int tx_cmd;
• debug(DRIVERNAME "[%s] Sending %u bytes\n", __FUNCTION__, length);
• /* frame size (words) */
• len = (length + 3) >> 2;
• bufp = (unsigned int *) (((u32)packet) & 0xFFFFFFFC);
• wrsz = (u32)length + 3;
• wrsz += ((u32)packet) & 0x3;
• wrsz >>= 2;
• tx_cmd = ((((unsigned int)(packet)) & 0x03) << 16) | (u32)length;
• /* check if there is enough room for the current frame */
• if (wrsz < (DNET_FIFO_SIZE - dnet_readl(dnet, TX_FIFO_WCNT))) {

• for (i = 0; i < wrsz; i++) {
  

• 	dnet_writel(dnet, *bufp++, TX_DATA_FIFO);
  

• }
  

• /*
  

•  * inform MAC that a packet's written and ready
  

•  * to be shipped out
  

•  */
  

• dnet_writel(dnet, tx_cmd, TX_LEN_FIFO);
  

• } else {

• printf(DRIVERNAME "No free space (actual %d, required %d "
  

• 		"(words))\n", DNET_FIFO_SIZE -
  

• 		dnet_readl(dnet, TX_FIFO_WCNT), wrsz);
  

• }
• /* No one cares anyway */
• return 0;

+}

+static int dnet_recv(struct eth_device *netdev) +{

• struct dnet_device *dnet = to_dnet(netdev);
• unsigned int * data_ptr;
• int pkt_len, poll, i;
• u32 cmd_word;
• debug("Waiting for pkt (polling)\n");
• poll = 50;
• while ((dnet_readl(dnet, RX_FIFO_WCNT) >> 16) == 0) {

• udelay(10);  // wait 10 usec
  

• --poll;
  

• if (poll == 0)
  
  

You can combine these two lines

• 	return 0;	// no pkt available
  

• }
• cmd_word = dnet_readl(dnet, RX_LEN_FIFO);
• pkt_len = cmd_word & 0xFFFF;
• debug("Got pkt with size %d bytes\n", pkt_len);
• if (cmd_word & 0xDF180000)

• printf("%s packet receive error %x\n", __FUNCTION__, cmd_word);
  

• data_ptr = (unsigned int *) NetRxPackets[0];
• for (i = 0; i < (pkt_len + 3) >> 2; i++)

• *data_ptr++ = dnet_readl(dnet, RX_DATA_FIFO);
  

• NetReceive(NetRxPackets[0], pkt_len + 5); /* ok + 5 ?? */
• return 0;

+}

+static void dnet_set_hwaddr(struct eth_device *netdev) +{

• struct dnet_device *dnet = to_dnet(netdev);
• u16 tmp;
• tmp = cpu_to_be16(*((u16 *)netdev->enetaddr));
• dnet_writew_mac(dnet, DNET_INTERNAL_MAC_ADDR_0_REG, tmp);
• tmp = cpu_to_be16(*((u16 *)(netdev->enetaddr + 2)));
• dnet_writew_mac(dnet, DNET_INTERNAL_MAC_ADDR_1_REG, tmp);
• tmp = cpu_to_be16(*((u16 *)(netdev->enetaddr + 4)));
• dnet_writew_mac(dnet, DNET_INTERNAL_MAC_ADDR_2_REG, tmp);

+}

+static void dnet_phy_reset(struct dnet_device *dnet) +{

• struct eth_device *netdev = &dnet->netdev;
• int i;
• u16 status, adv;
• adv = ADVERTISE_CSMA | ADVERTISE_ALL;
• dnet_mdio_write(dnet, MII_ADVERTISE, adv);
• printf("%s: Starting autonegotiation...\n", netdev->name);
• dnet_mdio_write(dnet, MII_BMCR, (BMCR_ANENABLE

• 			 | BMCR_ANRESTART));
  

• for (i = 0; i < CFG_DNET_AUTONEG_TIMEOUT / 100; i++) {

• status = dnet_mdio_read(dnet, MII_BMSR);
  

• if (status & BMSR_ANEGCOMPLETE)
  

• 	break;
  

• udelay(100);
  

• }
• if (status & BMSR_ANEGCOMPLETE)

• printf("%s: Autonegotiation complete\n", netdev->name);
  

• else

• printf("%s: Autonegotiation timed out (status=0x%04x)\n",
  

•        netdev->name, status);
  

+}

+static int dnet_phy_init(struct dnet_device *dnet) +{

• struct eth_device *netdev = &dnet->netdev;
• u16 phy_id, status, adv, lpa;
• int media, speed, duplex;
• int i;
• u32 ctl_reg;
• /* Find a PHY */
• for (i = 0; i < 32; i++) {

• dnet->phy_addr = i;
  

• phy_id = dnet_mdio_read(dnet, MII_PHYSID1);
  

• if (phy_id != 0xffff) {
  

• 	/* ok we found it */
  

• 	printf("Found PHY at address %d PHYID (%04x:%04x)\n",
  

• 			i, phy_id,
  

• 			dnet_mdio_read(dnet, MII_PHYSID2));
  

• 	break;
  

• }
  

• }
• /* Check if the PHY is up to snuff... */
• phy_id = dnet_mdio_read(dnet, MII_PHYSID1);
• if (phy_id == 0xffff) {

• printf("%s: No PHY present\n", netdev->name);
  

• return 0;
  
  

Convention is to return 0 on success, -1 on failure

• }
• status = dnet_mdio_read(dnet, MII_BMSR);
• if (!(status & BMSR_LSTATUS)) {

• /* Try to re-negotiate if we don't have link already. */
  

• dnet_phy_reset(dnet);
  

• for (i = 0; i < CFG_DNET_AUTONEG_TIMEOUT / 100; i++) {
  

• 	status = dnet_mdio_read(dnet, MII_BMSR);
  

• 	if (status & BMSR_LSTATUS)
  

• 		break;
  

• 	udelay(100);
  

• }
  

• }
• if (!(status & BMSR_LSTATUS)) {

• printf("%s: link down (status: 0x%04x)\n",
  

•        netdev->name, status);
  

• return 0;
  

• } else {

• adv = dnet_mdio_read(dnet, MII_ADVERTISE);
  

• lpa = dnet_mdio_read(dnet, MII_LPA);
  

• media = mii_nway_result(lpa & adv);
  

• speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
  

• 	 ? 1 : 0);
  

• duplex = (media & ADVERTISE_FULL) ? 1 : 0;
  

• /* 1000BaseT ethernet is not supported */
  

• printf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n",
  

•        netdev->name,
  

•        speed ? "100" : "10",
  

•        duplex ? "full" : "half",
  

•        lpa);
  

• ctl_reg = dnet_readw_mac(dnet, DNET_INTERNAL_RXTX_CONTROL_REG);
  

• if (duplex)
  

• 	ctl_reg &= ~(DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP);
  

• else
  

• 	ctl_reg |= DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP;
  

• dnet_writew_mac(dnet, DNET_INTERNAL_RXTX_CONTROL_REG, ctl_reg);
  

• return 1;
  

• }

+}

+static int dnet_init(struct eth_device *netdev, bd_t *bd) +{

• struct dnet_device *dnet = to_dnet(netdev);
• u32 config;
• /*

• * dnet_halt should have been called at some point before now,
  

• * so we'll assume the controller is idle.
  

• */
  

• /* set hardware address */
• dnet_set_hwaddr(netdev);
• if (!dnet_phy_init(dnet))

• return 0;
  

• /* flush rx/tx fifos */
• dnet_writel(dnet, DNET_SYS_CTL_RXFIFOFLUSH |

• 	DNET_SYS_CTL_TXFIFOFLUSH, SYS_CTL);
  

• udelay(1000);
• dnet_writel(dnet, 0, SYS_CTL);
• config = dnet_readw_mac(dnet, DNET_INTERNAL_RXTX_CONTROL_REG);
• config |= DNET_INTERNAL_RXTX_CONTROL_RXPAUSE |

• 	DNET_INTERNAL_RXTX_CONTROL_RXBROADCAST |
  

• 	DNET_INTERNAL_RXTX_CONTROL_DROPCONTROL |
  

• 	DNET_INTERNAL_RXTX_CONTROL_DISCFXFCS;
  

• dnet_writew_mac(dnet, DNET_INTERNAL_RXTX_CONTROL_REG, config);
• /* Enable TX and RX */
• dnet_writew_mac(dnet, DNET_INTERNAL_MODE_REG,

• 	DNET_INTERNAL_MODE_RXEN | DNET_INTERNAL_MODE_TXEN);
  

• return 1;

+}

+static void dnet_halt(struct eth_device *netdev) +{

• struct dnet_device *dnet = to_dnet(netdev);
• /* Disable TX and RX */
• dnet_writew_mac(dnet, DNET_INTERNAL_MODE_REG, 0);

+}

+int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr) +{

• struct dnet_device *dnet;
• struct eth_device *netdev;
• unsigned int dev_capa;
• dnet = malloc(sizeof(struct dnet_device));
• if (!dnet) {

• printf("Error: Failed to allocate memory for DNET%d\n", id);
  

• return -1;
  

• }
• memset(dnet, 0, sizeof(struct dnet_device));
• netdev = &dnet->netdev;
• dnet->regs = regs;
• dnet->phy_addr = phy_addr;
• sprintf(netdev->name, "dnet%d", id);
• netdev->init = dnet_init;
• netdev->halt = dnet_halt;
• netdev->send = dnet_send;
• netdev->recv = dnet_recv;
• dev_capa = dnet_readl(dnet, VERCAPS) & 0xFFFF;
• debug("%s: has %smdio, %sirq, %sgigabit, %sdma \n", netdev->name,

• (dev_capa & DNET_HAS_MDIO) ? "" : "no ",
  

• (dev_capa & DNET_HAS_IRQ) ? "" : "no ",
  

• (dev_capa & DNET_HAS_GIGABIT) ? "" : "no ",
  

• (dev_capa & DNET_HAS_DMA) ? "" : "no ");
  

• eth_register(netdev);
• return 0;

+}

+#endif /* CONFIG_CMD_NET */

+#endif /* CONFIG_DRIVER_DNET */ diff --git a/drivers/net/dnet.h b/drivers/net/dnet.h new file mode 100644 index 0000000..5bd4986 --- /dev/null +++ b/drivers/net/dnet.h @@ -0,0 +1,169 @@ +/*

• • Dave Ethernet Controller driver
• • Copyright (C) 2008 Dave S.r.l. <www.dave.eu>
• • This program is free software; you can redistribute it and/or modify
• • it under the terms of the GNU General Public License version 2 as
• • published by the Free Software Foundation.
• */

+#ifndef __DRIVERS_DNET_H__ +#define __DRIVERS_DNET_H__

+#define DRIVERNAME "dnet"

+/* Register access macros */ +#define dnet_writel(port, value, reg) \

• writel((value), (port)->regs + DNET_##reg)

+#define dnet_readl(port, reg) readl((port)->regs + DNET_##reg)

+/* ALL DNET FIFO REGISTERS */ +#define DNET_RX_LEN_FIFO (0x000) /* RX_LEN_FIFO */ +#define DNET_RX_DATA_FIFO (0x004) /* RX_DATA_FIFO */ +#define DNET_TX_LEN_FIFO (0x008) /* TX_LEN_FIFO */ +#define DNET_TX_DATA_FIFO (0x00C) /* TX_DATA_FIFO */

+/* ALL DNET CONTROL/STATUS REGISTERS OFFSETS */ +#define DNET_VERCAPS (0x100) /* VERCAPS */ +#define DNET_INTR_SRC (0x104) /* INTR_SRC */ +#define DNET_INTR_ENB (0x108) /* INTR_ENB */ +#define DNET_RX_STATUS (0x10C) /* RX_STATUS */ +#define DNET_TX_STATUS (0x110) /* TX_STATUS */ +#define DNET_RX_FRAMES_CNT (0x114) /* RX_FRAMES_CNT */ +#define DNET_TX_FRAMES_CNT (0x118) /* TX_FRAMES_CNT */ +#define DNET_RX_FIFO_TH (0x11C) /* RX_FIFO_TH */ +#define DNET_TX_FIFO_TH (0x120) /* TX_FIFO_TH */ +#define DNET_SYS_CTL (0x124) /* SYS_CTL */ +#define DNET_PAUSE_TMR (0x128) /* PAUSE_TMR */ +#define DNET_RX_FIFO_WCNT (0x12C) /* RX_FIFO_WCNT */ +#define DNET_TX_FIFO_WCNT (0x130) /* TX_FIFO_WCNT */

+/* ALL DNET MAC REGISTERS */ +#define DNET_MACREG_DATA (0x200) /* Mac-Reg Data */ +#define DNET_MACREG_ADDR (0x204) /* Mac-Reg Addr */

+/* ALL DNET RX STATISTICS COUNTERS */ +#define DNET_RX_PKT_IGNR_CNT (0x300) +#define DNET_RX_LEN_CHK_ERR_CNT (0x304) +#define DNET_RX_LNG_FRM_CNT (0x308) +#define DNET_RX_SHRT_FRM_CNT (0x30C) +#define DNET_RX_IPG_VIOL_CNT (0x310) +#define DNET_RX_CRC_ERR_CNT (0x314) +#define DNET_RX_OK_PKT_CNT (0x318) +#define DNET_RX_CTL_FRM_CNT (0x31C) +#define DNET_RX_PAUSE_FRM_CNT (0x320) +#define DNET_RX_MULTICAST_CNT (0x324) +#define DNET_RX_BROADCAST_CNT (0x328) +#define DNET_RX_VLAN_TAG_CNT (0x32C) +#define DNET_RX_PRE_SHRINK_CNT (0x330) +#define DNET_RX_DRIB_NIB_CNT (0x334) +#define DNET_RX_UNSUP_OPCD_CNT (0x338) +#define DNET_RX_BYTE_CNT (0x33C)

+/* DNET TX STATISTICS COUNTERS */ +#define DNET_TX_UNICAST_CNT (0x400) +#define DNET_TX_PAUSE_FRM_CNT (0x404) +#define DNET_TX_MULTICAST_CNT (0x408) +#define DNET_TX_BRDCAST_CNT (0x40C) +#define DNET_TX_VLAN_TAG_CNT (0x410) +#define DNET_TX_BAD_FCS_CNT (0x414) +#define DNET_TX_JUMBO_CNT (0x418) +#define DNET_TX_BYTE_CNT (0x41C)

+/* SOME INTERNAL MAC-CORE REGISTER */ +#define DNET_INTERNAL_MODE_REG (0x0) +#define DNET_INTERNAL_RXTX_CONTROL_REG (0x2) +#define DNET_INTERNAL_MAX_PKT_SIZE_REG (0x4) +#define DNET_INTERNAL_IGP_REG (0x8) +#define DNET_INTERNAL_MAC_ADDR_0_REG (0xa) +#define DNET_INTERNAL_MAC_ADDR_1_REG (0xc) +#define DNET_INTERNAL_MAC_ADDR_2_REG (0xe) +#define DNET_INTERNAL_TX_RX_STS_REG (0x12) +#define DNET_INTERNAL_GMII_MNG_CTL_REG (0x14) +#define DNET_INTERNAL_GMII_MNG_DAT_REG (0x16)

+#define DNET_INTERNAL_GMII_MNG_CMD_FIN (1 << 14)

+#define DNET_INTERNAL_WRITE (1 << 31)

+/* MAC-CORE REGISTER FIELDS */

+/* MAC-CORE MODE REGISTER FIELDS */ +#define DNET_INTERNAL_MODE_GBITEN (1 << 0) +#define DNET_INTERNAL_MODE_FCEN (1 << 1) +#define DNET_INTERNAL_MODE_RXEN (1 << 2) +#define DNET_INTERNAL_MODE_TXEN (1 << 3)

+/* MAC-CORE RXTX CONTROL REGISTER FIELDS */ +#define DNET_INTERNAL_RXTX_CONTROL_RXSHORTFRAME (1 << 8) +#define DNET_INTERNAL_RXTX_CONTROL_RXBROADCAST (1 << 7) +#define DNET_INTERNAL_RXTX_CONTROL_RXMULTICAST (1 << 4) +#define DNET_INTERNAL_RXTX_CONTROL_RXPAUSE (1 << 3) +#define DNET_INTERNAL_RXTX_CONTROL_DISTXFCS (1 << 2) +#define DNET_INTERNAL_RXTX_CONTROL_DISCFXFCS (1 << 1) +#define DNET_INTERNAL_RXTX_CONTROL_ENPROMISC (1 << 0) +#define DNET_INTERNAL_RXTX_CONTROL_DROPCONTROL (1 << 6) +#define DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP (1 << 5)

+/* SYSTEM CONTROL REGISTER FIELDS */ +#define DNET_SYS_CTL_IGNORENEXTPKT (1 << 0) +#define DNET_SYS_CTL_SENDPAUSE (1 << 2) +#define DNET_SYS_CTL_RXFIFOFLUSH (1 << 3) +#define DNET_SYS_CTL_TXFIFOFLUSH (1 << 4)

+/* TX STATUS REGISTER FIELDS */ +#define DNET_TX_STATUS_FIFO_ALMOST_EMPTY (1 << 2) +#define DNET_TX_STATUS_FIFO_ALMOST_FULL (1 << 1)

+/* INTERRUPT SOURCE REGISTER FIELDS */ +#define DNET_INTR_SRC_TX_PKTSENT (1 << 0) +#define DNET_INTR_SRC_TX_FIFOAF (1 << 1) +#define DNET_INTR_SRC_TX_FIFOAE (1 << 2) +#define DNET_INTR_SRC_TX_DISCFRM (1 << 3) +#define DNET_INTR_SRC_TX_FIFOFULL (1 << 4) +#define DNET_INTR_SRC_RX_CMDFIFOAF (1 << 8) +#define DNET_INTR_SRC_RX_CMDFIFOFF (1 << 9) +#define DNET_INTR_SRC_RX_DATAFIFOFF (1 << 10) +#define DNET_INTR_SRC_TX_SUMMARY (1 << 16) +#define DNET_INTR_SRC_RX_SUMMARY (1 << 17) +#define DNET_INTR_SRC_PHY (1 << 19)

+/* INTERRUPT ENABLE REGISTER FIELDS */ +#define DNET_INTR_ENB_TX_PKTSENT (1 << 0) +#define DNET_INTR_ENB_TX_FIFOAF (1 << 1) +#define DNET_INTR_ENB_TX_FIFOAE (1 << 2) +#define DNET_INTR_ENB_TX_DISCFRM (1 << 3) +#define DNET_INTR_ENB_TX_FIFOFULL (1 << 4) +#define DNET_INTR_ENB_RX_PKTRDY (1 << 8) +#define DNET_INTR_ENB_RX_FIFOAF (1 << 9) +#define DNET_INTR_ENB_RX_FIFOERR (1 << 10) +#define DNET_INTR_ENB_RX_ERROR (1 << 11) +#define DNET_INTR_ENB_RX_FIFOFULL (1 << 12) +#define DNET_INTR_ENB_RX_FIFOAE (1 << 13) +#define DNET_INTR_ENB_TX_SUMMARY (1 << 16) +#define DNET_INTR_ENB_RX_SUMMARY (1 << 17) +#define DNET_INTR_ENB_GLOBAL_ENABLE (1 << 18)

+/*

• • Capabilities. Used by the driver to know the capabilities that
• • the ethernet controller inside the FPGA have.
• */

+#define DNET_HAS_MDIO (1 << 0) +#define DNET_HAS_IRQ (1 << 1) +#define DNET_HAS_GIGABIT (1 << 2) +#define DNET_HAS_DMA (1 << 3)

+#define DNET_HAS_MII (1 << 4) // or GMII +#define DNET_HAS_RMII (1 << 5) // or RGMII

+#define DNET_CAPS_MASK 0xFFFF

+#define DNET_FIFO_SIZE 2048 /* 2K x 32 bit */ +#define DNET_FIFO_TX_DATA_AF_TH (DNET_FIFO_SIZE - 384) /* 384 = 1536 / 4 */ +#define DNET_FIFO_TX_DATA_AE_TH (384)

+#define DNET_FIFO_RX_CMD_AF_TH (1 << 16) /* just one frame inside the FIFO */

+#endif

regards, Ben