The RZ/N1 is a family of SoC devices from Renesas [1], featuring ARM Cortex-A7 and/or Cortex-M3 CPU, industrial ethernet protocols, integrated Ethernet switch, and numerous peripherals.
This is a first step in upstreaming support for the RZ/N1 family. Currently it contains just enough to boot to the u-boot prompt. Additional patches will follow to support flash, SD, USB, Ethernet, etc.
At this point, I am looking for general feedback about the overall direction and structure. I'm aware of several checkpatch warnings, and some TODO/FIXME items, which will be addressed.
This work is based on a vendor-supplied u-boot 2017.01 tree [2], which supports several eval boards, none of which I have access to. Instead development has been done on a Schneider LCES2 board, which is fairly similar to the Renesas RZ/N1D-DB Demo board.
The patches are currently against v2022.10-rc2.
[1] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-m... [2] https://github.com/renesas-rz/rzn1_u-boot/tree/rzn1-stable
Michel Pollet (1): tools: Add tool to create Renesas SPKG images
Ralph Siemsen (8): ARM: armv7: add non-SPL enable for Cortex SMPEN clk: renesas: prepare for non-RCAR clock drivers clk: renesas: add R906G032 driver pinctrl: renesas: add R906G032 driver ram: cadence: add driver for Cadence EDAC dts: basic devicetree for Renesas RZ/N1 SoC ARM: rzn1: basic support for Renesas RZ/N1 SoC board: schneider: add LCES board support
arch/arm/Kconfig | 17 + arch/arm/Makefile | 1 + arch/arm/cpu/armv7/Kconfig | 5 + arch/arm/dts/r9a06g032-rzn1d400-lces.dts | 50 ++ arch/arm/dts/r9a06g032.dtsi | 225 ++++++ arch/arm/mach-rzn1/Kconfig | 32 + arch/arm/mach-rzn1/Makefile | 3 + arch/arm/mach-rzn1/cpu_info.c | 20 + board/schneider/lces/Kconfig | 12 + board/schneider/lces/Makefile | 3 + board/schneider/lces/ddr_timing.c | 140 ++++ .../lces/jedec_ddr3_2g_x16_1333h_500_cl8.h | 399 ++++++++++ board/schneider/lces/lces.c | 41 + configs/lces_defconfig | 26 + drivers/clk/renesas/Kconfig | 8 +- drivers/clk/renesas/Makefile | 6 +- drivers/clk/renesas/r9a06g032-clocks.c | 734 ++++++++++++++++++ drivers/pinctrl/Makefile | 1 + drivers/pinctrl/renesas/Kconfig | 7 + drivers/pinctrl/renesas/Makefile | 1 + drivers/pinctrl/renesas/pinctrl-rzn1.c | 398 ++++++++++ drivers/ram/Kconfig | 1 + drivers/ram/Makefile | 2 + drivers/ram/cadence/Kconfig | 24 + drivers/ram/cadence/Makefile | 1 + drivers/ram/cadence/ddr_async.c | 295 +++++++ drivers/ram/cadence/ddr_ctrl.c | 414 ++++++++++ drivers/ram/cadence/ddr_ctrl.h | 172 ++++ include/configs/lces.h | 22 + include/dt-bindings/clock/r9a06g032-sysctrl.h | 148 ++++ include/dt-bindings/pinctrl/rzn1-pinctrl.h | 141 ++++ tools/Makefile | 2 + tools/spkg_header.h | 49 ++ tools/spkg_utility.c | 306 ++++++++ 34 files changed, 3702 insertions(+), 4 deletions(-) create mode 100644 arch/arm/dts/r9a06g032-rzn1d400-lces.dts create mode 100644 arch/arm/dts/r9a06g032.dtsi create mode 100644 arch/arm/mach-rzn1/Kconfig create mode 100644 arch/arm/mach-rzn1/Makefile create mode 100644 arch/arm/mach-rzn1/cpu_info.c create mode 100644 board/schneider/lces/Kconfig create mode 100644 board/schneider/lces/Makefile create mode 100644 board/schneider/lces/ddr_timing.c create mode 100644 board/schneider/lces/jedec_ddr3_2g_x16_1333h_500_cl8.h create mode 100644 board/schneider/lces/lces.c create mode 100644 configs/lces_defconfig create mode 100644 drivers/clk/renesas/r9a06g032-clocks.c create mode 100644 drivers/pinctrl/renesas/pinctrl-rzn1.c create mode 100644 drivers/ram/cadence/Kconfig create mode 100644 drivers/ram/cadence/Makefile create mode 100644 drivers/ram/cadence/ddr_async.c create mode 100644 drivers/ram/cadence/ddr_ctrl.c create mode 100644 drivers/ram/cadence/ddr_ctrl.h create mode 100644 include/configs/lces.h create mode 100644 include/dt-bindings/clock/r9a06g032-sysctrl.h create mode 100644 include/dt-bindings/pinctrl/rzn1-pinctrl.h create mode 100644 tools/spkg_header.h create mode 100644 tools/spkg_utility.c