From: Eugen Hristev eugen.hristev@microchip.com
Implement the lpddr2 initialization procedure for at91 mpddrc multi-port ddram controller.
Signed-off-by: Eugen Hristev eugen.hristev@microchip.com --- arch/arm/mach-at91/include/mach/atmel_mpddrc.h | 23 ++++ arch/arm/mach-at91/mpddrc.c | 162 +++++++++++++++++++++++++ 2 files changed, 185 insertions(+)
diff --git a/arch/arm/mach-at91/include/mach/atmel_mpddrc.h b/arch/arm/mach-at91/include/mach/atmel_mpddrc.h index 45a76a6..40ec87e 100644 --- a/arch/arm/mach-at91/include/mach/atmel_mpddrc.h +++ b/arch/arm/mach-at91/include/mach/atmel_mpddrc.h @@ -18,6 +18,9 @@ struct atmel_mpddrc_config { u32 tpr1; u32 tpr2; u32 md; + u32 lpddr23_lpr; + u32 cal_mr4; + u32 tim_cal; };
/* @@ -61,6 +64,10 @@ int ddr2_init(const unsigned int base, const unsigned int ram_address, const struct atmel_mpddrc_config *mpddr_value);
+int lpddr2_init(const unsigned int base, + const unsigned int ram_address, + const struct atmel_mpddrc_config *mpddr_value); + int ddr3_init(const unsigned int base, const unsigned int ram_address, const struct atmel_mpddrc_config *mpddr_value); @@ -74,6 +81,11 @@ int ddr3_init(const unsigned int base, #define ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD 0x5 #define ATMEL_MPDDRC_MR_MODE_DEEP_CMD 0x6 #define ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD 0x7 +#define ATMEL_MPDDRC_MR_MRS(v) (((v) & 0xFF) << 0x8) + +/* Bit field in refresh timer register */ +#define ATMEL_MPDDRC_RTR_ADJ_REF (0x1 << 16) +#define ATMEL_MPDDRC_RTR_MR4VALUE(v) (((v) & 0x7) << 20)
/* Bit field in configuration register */ #define ATMEL_MPDDRC_CR_NC_MASK 0x3 @@ -157,6 +169,7 @@ int ddr3_init(const unsigned int base, #define ATMEL_MPDDRC_MD_DDR3_SDRAM 0x4 #define ATMEL_MPDDRC_MD_LPDDR3_SDRAM 0x5 #define ATMEL_MPDDRC_MD_DDR2_SDRAM 0x6 +#define ATMEL_MPDDRC_MD_LPDDR2_SDRAM 0x7 #define ATMEL_MPDDRC_MD_DBW_MASK (0x1 << 4) #define ATMEL_MPDDRC_MD_DBW_32_BITS (0x0 << 4) #define ATMEL_MPDDRC_MD_DBW_16_BITS (0x1 << 4) @@ -206,4 +219,14 @@ int ddr3_init(const unsigned int base, #define ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_TWO_CYCLE 0x2 #define ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_THREE_CYCLE 0x3
+/* Bit field in LPDDR2 - LPDDR3 Low Power Register */ +#define ATMEL_MPDDRC_LPDDR23_LPR_DS(x) (((x) & 0xf) << 24) + +/* Bit field in CAL_MR4 Calibration and MR4 Register */ +#define ATMEL_MPDDRC_CAL_MR4_COUNT_CAL(x) (((x) & 0xffff) << 0) +#define ATMEL_MPDDRC_CAL_MR4_MR4R(x) (((x) & 0xffff) << 16) + +/* Bit field in TIM_CAL Timing Calibration Register */ +#define ATMEL_MPDDRC_CALR_ZQCS(x) (((x) & 0xff) << 0) + #endif diff --git a/arch/arm/mach-at91/mpddrc.c b/arch/arm/mach-at91/mpddrc.c index 81ccd6a..3df0ea7 100644 --- a/arch/arm/mach-at91/mpddrc.c +++ b/arch/arm/mach-at91/mpddrc.c @@ -10,6 +10,7 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/atmel_mpddrc.h> +#include <asm/arch/at91_common.h>
#define SAMA5D3_MPDDRC_VERSION 0x140
@@ -18,6 +19,7 @@ static inline void atmel_mpddr_op(const struct atmel_mpddr *mpddr, u32 ram_address) { writel(mode, &mpddr->mr); + dmb(); writel(0, ram_address); }
@@ -227,3 +229,163 @@ int ddr3_init(const unsigned int base,
return 0; } + +int lpddr2_init(const unsigned int base, + const unsigned int ram_address, + const struct atmel_mpddrc_config *mpddr_value) +{ + struct atmel_mpddr *mpddr = (struct atmel_mpddr *)base; + u32 reg; + + writel(mpddr_value->lpddr23_lpr, &mpddr->lpddr23_lpr); + + writel(mpddr_value->tim_cal, &mpddr->tim_cal); + + /* 1. Program the memory device type */ + writel(mpddr_value->md, &mpddr->md); + + /* + * 2. Program features of the LPDDR2-SDRAM device and timing parameters + */ + writel(mpddr_value->cr, &mpddr->cr); + + writel(mpddr_value->tpr0, &mpddr->tpr0); + writel(mpddr_value->tpr1, &mpddr->tpr1); + writel(mpddr_value->tpr2, &mpddr->tpr2); + + /* 3. A NOP command is issued to the LPDDR2-SDRAM */ + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address); + + /* + * 3bis. Add memory barrier then Perform a write access to + * any low-power DDR2-SDRAM address to acknowledge the command. + */ + + dmb(); + writel(0, ram_address); + + /* 4. A pause of at least 100 ns must be observed before a single toggle */ + udelay(1); + + /* 5. A NOP command is issued to the LPDDR2-SDRAM */ + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address); + + /* 6. A pause of at least 200 us must be observed before a Reset Command */ + udelay(200); + + /* 7. A Reset command is issued to the low-power DDR2-SDRAM. */ + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD | + ATMEL_MPDDRC_MR_MRS(63), ram_address); + + /* + * 8. A pause of at least tINIT5 must be observed before issuing + * any commands + */ + udelay(1); + + /* 9. A Calibration command is issued to the low-power DDR2-SDRAM. */ + reg = readl(&mpddr->cr); + reg &= ~ATMEL_MPDDRC_CR_ZQ_RESET; + reg |= ATMEL_MPDDRC_CR_ZQ_RESET; + writel(reg, &mpddr->cr); + + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD | + ATMEL_MPDDRC_MR_MRS(10), ram_address); + + /* + * 9bis: The ZQ Calibration command is now issued. + * Program the type of calibration in the MPDDRC_CR: set the + * ZQ field to the SHORT value. + */ + reg = readl(&mpddr->cr); + reg &= ~ATMEL_MPDDRC_CR_ZQ_RESET; + reg |= ATMEL_MPDDRC_CR_ZQ_SHORT; + writel(reg, &mpddr->cr); + + /* + * 10: A Mode Register Write command with 1 to the MRS field + * is issued to the low-power DDR2-SDRAM. + */ + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD | + ATMEL_MPDDRC_MR_MRS(1), ram_address); + + /* + * 11: A Mode Register Write command with 2 to the MRS field + * is issued to the low-power DDR2-SDRAM. + */ + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD | + ATMEL_MPDDRC_MR_MRS(2), ram_address); + + /* + * 12: A Mode Register Write command with 3 to the MRS field + * is issued to the low-power DDR2-SDRAM. + */ + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD | + ATMEL_MPDDRC_MR_MRS(3), ram_address); + + /* + * 13: A Mode Register Write command with 16 to the MRS field + * is issued to the low-power DDR2-SDRAM. + */ + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD | + ATMEL_MPDDRC_MR_MRS(16), ram_address); + + /* + * 14: In the DDR Configuration Register, open the input buffers. + */ +#ifdef CONFIG_ATMEL_SFR + configure_ddrcfg_input_buffers(true); +#endif + + /* 15. A NOP command is issued to the LPDDR2-SDRAM */ + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address); + + /* + * 16: A Mode Register Write command with 5 to the MRS field + * is issued to the low-power DDR2-SDRAM. + */ + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD | + ATMEL_MPDDRC_MR_MRS(5), ram_address); + + /* + * 17: A Mode Register Write command with 6 to the MRS field + * is issued to the low-power DDR2-SDRAM. + */ + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD | + ATMEL_MPDDRC_MR_MRS(6), ram_address); + + /* + * 18: A Mode Register Write command with 8 to the MRS field + * is issued to the low-power DDR2-SDRAM. + */ + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD | + ATMEL_MPDDRC_MR_MRS(8), ram_address); + + /* + * 19: A Mode Register Write command with 0 to the MRS field + * is issued to the low-power DDR2-SDRAM. + */ + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD | + ATMEL_MPDDRC_MR_MRS(0), ram_address); + + /* + * 20: A Normal Mode command is provided. + */ + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NORMAL_CMD, ram_address); + + /* 21: In the DDR Configuration Register, close the input buffers. */ +#ifdef CONFIG_ATMEL_SFR + configure_ddrcfg_input_buffers(false); +#endif + + /* + * 22: Write the refresh rate into the COUNT field in the MPDDRC + * Refresh Timer Register. + */ + writel(mpddr_value->rtr, &mpddr->rtr); + + /* 23. Configre CAL MR4 register */ + writel(mpddr_value->cal_mr4, &mpddr->cal_mr4); + + return 0; +}