On Thursday 30 April 2009, Jean-Christophe PLAGNIOL-VILLARD wrote:
On 23:35 Wed 29 Apr , David Brownell wrote:
On Wednesday 29 April 2009, Jean-Christophe PLAGNIOL-VILLARD wrote:
my idea is more this the lowlovel will init the pll (lowlevel_init.S or other stage bootloader)
Right ...
so instead of hardcoding the PPLDIV read it in the register and then calculate the clock rate
That's all this code does: read the PLL registers (and divider taps), and display settings in use by the current board.
yes but it's does not provice help full api to use it other where in the code
Use it where/why? There's not been a need for anything analagous to <linux/clk.h> ...
It happens that some SoCs have slightly different PLL configuration (like pre/post dividers) and feed important components (ARM, DSP, DDR) from different PLL dividers.
the PLL dividers are hardcoded why?
A few are hard-wired in silicon, others are programmable. Either way, they rarely change after lowlevel init.
Mostly it's a case of *which* divider -- DIV1, DIV2, DIV4, etc. Each divider feeds a fixed set of modules, and different SoCs map them differently: fixed/not, which modules, allowable frequency ranges, etc.
It happens that the cases U-Boot cares about today bypass the PLL and dividers entirely: clocks going to timer and the UART directly match the main xtal. Or, like USB, the exact clock rate is either hard wired (60 MHz for the PHY) or doesn't matter.
- Dave