Perform a simple rename of CONFIG_MAX_MEM_MAPPED to CFG_MAX_MEM_MAPPED
Signed-off-by: Tom Rini trini@konsulko.com --- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 6 +++--- arch/arm/include/asm/arch-fsl-layerscape/config.h | 14 +++++++------- arch/arm/include/asm/arch-ls102xa/config.h | 2 +- arch/powerpc/cpu/mpc85xx/cpu.c | 14 +++++++------- arch/powerpc/cpu/mpc85xx/mp.c | 4 ++-- arch/powerpc/cpu/mpc85xx/tlb.c | 8 ++++---- arch/powerpc/cpu/mpc8xxx/pamu_table.c | 2 +- arch/powerpc/include/asm/config.h | 6 +++--- arch/xtensa/include/asm/config.h | 2 +- board/ti/dra7xx/evm.c | 14 +++++++------- common/memsize.c | 6 +++--- drivers/ddr/fsl/util.c | 6 +++--- include/configs/dra7xx_evm.h | 2 +- include/configs/mt7621.h | 2 +- include/configs/rcar-gen3-common.h | 2 +- include/configs/synquacer.h | 2 +- include/configs/xtfpga.h | 8 ++++---- 17 files changed, 50 insertions(+), 50 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 2aeec7dea7bf..5c45c2a5ed58 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -1308,13 +1308,13 @@ phys_size_t get_effective_memsize(void) * allocated from first region. If the memory extends to the second * region (or the third region if applicable), Management Complex (MC) * memory should be put into the highest region, i.e. the end of DDR - * memory. CONFIG_MAX_MEM_MAPPED is set to the size of first region so + * memory. CFG_MAX_MEM_MAPPED is set to the size of first region so * U-Boot doesn't relocate itself into higher address. Should DDR be * configured to skip the first region, this function needs to be * adjusted. */ - if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) { - ea_size = CONFIG_MAX_MEM_MAPPED; + if (gd->ram_size > CFG_MAX_MEM_MAPPED) { + ea_size = CFG_MAX_MEM_MAPPED; rem = gd->ram_size - ea_size; } else { ea_size = gd->ram_size; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 57d92f65520d..12758c8dd1ca 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -36,7 +36,7 @@
/* DDR */ #define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE +#define CFG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE
/* Generic Interrupt Controller Definitions */ #define GICD_BASE 0x06000000 @@ -121,7 +121,7 @@
/* DDR */ #define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE +#define CFG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE
/* DCFG - GUR */ #define CFG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ @@ -147,7 +147,7 @@
/* DDR */ #define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE +#define CFG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE
/* Generic Interrupt Controller Definitions */ #define GICD_BASE 0x06000000 @@ -191,7 +191,7 @@
/* DDR */ #define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE +#define CFG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE
/* SEC */
@@ -211,7 +211,7 @@ #define CFG_SYS_NUM_FM1_DTSEC 7 #define CFG_SYS_NUM_FM1_10GEC 1 #define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE +#define CFG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE
#define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 @@ -250,14 +250,14 @@ #define GICD_BASE 0x01401000 #define GICC_BASE 0x01402000 #define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE +#define CFG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE
#elif defined(CONFIG_ARCH_LS1046A) #define CFG_SYS_NUM_FMAN 1 #define CFG_SYS_NUM_FM1_DTSEC 8 #define CFG_SYS_NUM_FM1_10GEC 2 #define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE +#define CFG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE
/* SMMU Defintions */ #define SMMU_BASE 0x09000000 diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index 4a4d64244148..d0abbdadf08b 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -70,7 +70,7 @@ /* SATA */ #define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000) #ifdef CONFIG_DDR_SPD -#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30) +#define CFG_MAX_MEM_MAPPED ((phys_size_t)2 << 30) #endif
#define DCU_LAYER_MAX_NUM 16 diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index be85c54e4801..0abcc01b8574 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -616,12 +616,12 @@ static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset) /* * slide the testing window up to test another area * for 32_bit system, the maximum testable memory is limited to - * CONFIG_MAX_MEM_MAPPED + * CFG_MAX_MEM_MAPPED */ int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset) { phys_addr_t test_cap, p_addr; - phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED); + phys_size_t p_size = min(gd->ram_size, CFG_MAX_MEM_MAPPED);
#if !defined(CONFIG_PHYS_64BIT) || \ !defined(CFG_SYS_INIT_RAM_ADDR_PHYS) || \ @@ -632,7 +632,7 @@ int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset) #endif p_addr = (*vstart) + (*size) + (*phys_offset); if (p_addr < test_cap - 1) { - p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED); + p_size = min(test_cap - p_addr, CFG_MAX_MEM_MAPPED); if (reset_tlb(p_addr, p_size, phys_offset) == -1) return -1; *vstart = CFG_SYS_DDR_SDRAM_BASE; @@ -649,18 +649,18 @@ int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset) /* initialization for testing area */ int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) { - phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED); + phys_size_t p_size = min(gd->ram_size, CFG_MAX_MEM_MAPPED);
*vstart = CFG_SYS_DDR_SDRAM_BASE; - *size = (u32) p_size; /* CONFIG_MAX_MEM_MAPPED < 4G */ + *size = (u32) p_size; /* CFG_MAX_MEM_MAPPED < 4G */ *phys_offset = 0;
#if !defined(CONFIG_PHYS_64BIT) || \ !defined(CFG_SYS_INIT_RAM_ADDR_PHYS) || \ (CFG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) - if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) { + if (gd->ram_size > CFG_MAX_MEM_MAPPED) { puts("Cannot test more than "); - print_size(CONFIG_MAX_MEM_MAPPED, + print_size(CFG_MAX_MEM_MAPPED, " without proper 36BIT support.\n"); } #endif diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c index 44f8ed8a19a3..7c47e415f05d 100644 --- a/arch/powerpc/cpu/mpc85xx/mp.c +++ b/arch/powerpc/cpu/mpc85xx/mp.c @@ -193,8 +193,8 @@ u32 determine_mp_bootpg(unsigned int *pagesize)
/* use last 4K of mapped memory */ - bootpg = ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ? - CONFIG_MAX_MEM_MAPPED : gd->ram_size) + + bootpg = ((gd->ram_size > CFG_MAX_MEM_MAPPED) ? + CFG_MAX_MEM_MAPPED : gd->ram_size) + CFG_SYS_SDRAM_BASE - 4096; if (pagesize) *pagesize = 4096; diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c index 5d21bef58781..2a78f0fe502c 100644 --- a/arch/powerpc/cpu/mpc85xx/tlb.c +++ b/arch/powerpc/cpu/mpc85xx/tlb.c @@ -306,12 +306,12 @@ unsigned int setup_ddr_tlbs_phys(phys_addr_t p_addr, u64 memsize = (u64)memsize_in_meg << 20; u64 size;
- size = min(memsize, (u64)CONFIG_MAX_MEM_MAPPED); + size = min(memsize, (u64)CFG_MAX_MEM_MAPPED); size = tlb_map_range(ram_tlb_address, p_addr, size, TLB_MAP_RAM);
- if (size || memsize > CONFIG_MAX_MEM_MAPPED) { - print_size(memsize > CONFIG_MAX_MEM_MAPPED ? - memsize - CONFIG_MAX_MEM_MAPPED + size : size, + if (size || memsize > CFG_MAX_MEM_MAPPED) { + print_size(memsize > CFG_MAX_MEM_MAPPED ? + memsize - CFG_MAX_MEM_MAPPED + size : size, " of DDR memory left unmapped in U-Boot\n"); #ifndef CONFIG_SPL_BUILD puts(" "); diff --git a/arch/powerpc/cpu/mpc8xxx/pamu_table.c b/arch/powerpc/cpu/mpc8xxx/pamu_table.c index caad6670cc90..b906279226a5 100644 --- a/arch/powerpc/cpu/mpc8xxx/pamu_table.c +++ b/arch/powerpc/cpu/mpc8xxx/pamu_table.c @@ -17,7 +17,7 @@ void construct_pamu_addr_table(struct pamu_addr_tbl *tbl, int *num_entries)
tbl->start_addr[i] = (uint64_t)virt_to_phys((void *)CFG_SYS_SDRAM_BASE); - tbl->size[i] = (phys_size_t)(min(gd->ram_size, CONFIG_MAX_MEM_MAPPED)); + tbl->size[i] = (phys_size_t)(min(gd->ram_size, CFG_MAX_MEM_MAPPED)); tbl->end_addr[i] = tbl->start_addr[i] + tbl->size[i] - 1;
i++; diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h index 983c6f70cfee..f0702cab1431 100644 --- a/arch/powerpc/include/asm/config.h +++ b/arch/powerpc/include/asm/config.h @@ -14,13 +14,13 @@ #define HWCONFIG_BUFFER_SIZE 256 #endif
-#ifndef CONFIG_MAX_MEM_MAPPED +#ifndef CFG_MAX_MEM_MAPPED #if defined(CONFIG_E500) || \ defined(CONFIG_MPC86xx) || \ defined(CONFIG_E300) -#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30) +#define CFG_MAX_MEM_MAPPED ((phys_size_t)2 << 30) #else -#define CONFIG_MAX_MEM_MAPPED (256 << 20) +#define CFG_MAX_MEM_MAPPED (256 << 20) #endif #endif
diff --git a/arch/xtensa/include/asm/config.h b/arch/xtensa/include/asm/config.h index 21b334b93896..268c5688b3d3 100644 --- a/arch/xtensa/include/asm/config.h +++ b/arch/xtensa/include/asm/config.h @@ -14,7 +14,7 @@ * restricting used physical memory to the first 128MB. */ #if XCHAL_HAVE_PTP_MMU -#define CONFIG_MAX_MEM_MAPPED (128 << 20) +#define CFG_MAX_MEM_MAPPED (128 << 20) #endif
#endif diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 1c00e253ffc8..bd7aac3656a6 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -279,13 +279,13 @@ void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) case DRA752_ES2_0: switch (emif_nr) { case 1: - if (ram_size > CONFIG_MAX_MEM_MAPPED) + if (ram_size > CFG_MAX_MEM_MAPPED) *regs = &emif1_ddr3_532_mhz_1cs_2G; else *regs = &emif1_ddr3_532_mhz_1cs; break; case 2: - if (ram_size > CONFIG_MAX_MEM_MAPPED) + if (ram_size > CFG_MAX_MEM_MAPPED) *regs = &emif2_ddr3_532_mhz_1cs_2G; else *regs = &emif2_ddr3_532_mhz_1cs; @@ -303,7 +303,7 @@ void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) case DRA722_ES1_0: case DRA722_ES2_0: case DRA722_ES2_1: - if (ram_size < CONFIG_MAX_MEM_MAPPED) + if (ram_size < CFG_MAX_MEM_MAPPED) *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1; else *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es2; @@ -362,7 +362,7 @@ void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) case DRA752_ES1_0: case DRA752_ES1_1: case DRA752_ES2_0: - if (ram_size > CONFIG_MAX_MEM_MAPPED) + if (ram_size > CFG_MAX_MEM_MAPPED) *dmm_lisa_regs = &lisa_map_dra7_2GB; else *dmm_lisa_regs = &lisa_map_dra7_1536MB; @@ -371,7 +371,7 @@ void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) case DRA722_ES2_0: case DRA722_ES2_1: default: - if (ram_size < CONFIG_MAX_MEM_MAPPED) + if (ram_size < CFG_MAX_MEM_MAPPED) *dmm_lisa_regs = &lisa_map_2G_x_2; else *dmm_lisa_regs = &lisa_map_2G_x_4; @@ -646,9 +646,9 @@ int dram_init_banksize(void)
gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = get_effective_memsize(); - if (ram_size > CONFIG_MAX_MEM_MAPPED) { + if (ram_size > CFG_MAX_MEM_MAPPED) { gd->bd->bi_dram[1].start = 0x200000000; - gd->bd->bi_dram[1].size = ram_size - CONFIG_MAX_MEM_MAPPED; + gd->bd->bi_dram[1].size = ram_size - CFG_MAX_MEM_MAPPED; }
return 0; diff --git a/common/memsize.c b/common/memsize.c index 3c80ad2c8346..ad9ddf67ac5b 100644 --- a/common/memsize.c +++ b/common/memsize.c @@ -106,11 +106,11 @@ phys_size_t __weak get_effective_memsize(void) if (gd->ram_base + ram_size < gd->ram_base) ram_size = ((phys_size_t)~0xfffULL) - gd->ram_base;
-#ifndef CONFIG_MAX_MEM_MAPPED +#ifndef CFG_MAX_MEM_MAPPED return ram_size; #else /* limit stack to what we can reasonable map */ - return ((ram_size > CONFIG_MAX_MEM_MAPPED) ? - CONFIG_MAX_MEM_MAPPED : ram_size); + return ((ram_size > CFG_MAX_MEM_MAPPED) ? + CFG_MAX_MEM_MAPPED : ram_size); #endif } diff --git a/drivers/ddr/fsl/util.c b/drivers/ddr/fsl/util.c index e49cf6e8e3db..60051392e713 100644 --- a/drivers/ddr/fsl/util.c +++ b/drivers/ddr/fsl/util.c @@ -139,10 +139,10 @@ __fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params, }
#if !defined(CONFIG_PHYS_64BIT) - if (base >= CONFIG_MAX_MEM_MAPPED) + if (base >= CFG_MAX_MEM_MAPPED) return; - if ((base + size) >= CONFIG_MAX_MEM_MAPPED) - size = CONFIG_MAX_MEM_MAPPED - base; + if ((base + size) >= CFG_MAX_MEM_MAPPED) + size = CFG_MAX_MEM_MAPPED - base; #endif if (set_ddr_laws(base, size, law_memctl) < 0) { printf("%s: ERROR (ctrl #%d, TRGT ID=%x)\n", __func__, ctrl_num, diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index f8afcc7826e9..ef1d5a112608 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -13,7 +13,7 @@
#include <environment/ti/dfu.h>
-#define CONFIG_MAX_MEM_MAPPED 0x80000000 +#define CFG_MAX_MEM_MAPPED 0x80000000
#ifndef CONFIG_QSPI_BOOT /* MMC ENV related defines */ diff --git a/include/configs/mt7621.h b/include/configs/mt7621.h index b6e680bcc78e..a9574940d42f 100644 --- a/include/configs/mt7621.h +++ b/include/configs/mt7621.h @@ -10,7 +10,7 @@
#define CFG_SYS_SDRAM_BASE 0x80000000
-#define CONFIG_MAX_MEM_MAPPED 0x1c000000 +#define CFG_MAX_MEM_MAPPED 0x1c000000
#define CFG_SYS_INIT_SP_OFFSET 0x800000
diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h index 8e0837a30275..213caa75238a 100644 --- a/include/configs/rcar-gen3-common.h +++ b/include/configs/rcar-gen3-common.h @@ -28,7 +28,7 @@ #define DRAM_RSV_SIZE 0x08000000 #define CFG_SYS_SDRAM_BASE (0x40000000 + DRAM_RSV_SIZE) #define CFG_SYS_SDRAM_SIZE (0x80000000u - DRAM_RSV_SIZE) -#define CONFIG_MAX_MEM_MAPPED (0x80000000u - DRAM_RSV_SIZE) +#define CFG_MAX_MEM_MAPPED (0x80000000u - DRAM_RSV_SIZE)
/* ENV setting */
diff --git a/include/configs/synquacer.h b/include/configs/synquacer.h index a62d1d325478..e65d6238163f 100644 --- a/include/configs/synquacer.h +++ b/include/configs/synquacer.h @@ -14,7 +14,7 @@ #define CFG_SYS_SDRAM_BASE (0x80000000) /* Start address of DDR3 */ #define PHYS_SDRAM_SIZE (0x7c000000) /* Default size (2GB - Secure memory) */
-#define CONFIG_MAX_MEM_MAPPED PHYS_SDRAM_SIZE +#define CFG_MAX_MEM_MAPPED PHYS_SDRAM_SIZE
#define SQ_DRAMINFO_BASE (0x2e00ffc0) /* DRAM info from TF-A */
diff --git a/include/configs/xtfpga.h b/include/configs/xtfpga.h index 83a0539d8f2d..9655b666eda7 100644 --- a/include/configs/xtfpga.h +++ b/include/configs/xtfpga.h @@ -27,7 +27,7 @@ #else #define CFG_SYS_MEMORY_BASE 0x60000000 #define CFG_SYS_IO_BASE 0x90000000 -#define CONFIG_MAX_MEM_MAPPED 0x10000000 +#define CFG_MAX_MEM_MAPPED 0x10000000 #endif
/* Onboard RAM sizes: @@ -53,10 +53,10 @@
/* Memory test is destructive so default must not overlap vectors or U-Boot*/
-#if defined(CONFIG_MAX_MEM_MAPPED) && \ - CONFIG_MAX_MEM_MAPPED < CFG_SYS_SDRAM_SIZE +#if defined(CFG_MAX_MEM_MAPPED) && \ + CFG_MAX_MEM_MAPPED < CFG_SYS_SDRAM_SIZE #define XTENSA_SYS_TEXT_ADDR \ - (MEMADDR(CONFIG_MAX_MEM_MAPPED) - CONFIG_SYS_MONITOR_LEN) + (MEMADDR(CFG_MAX_MEM_MAPPED) - CONFIG_SYS_MONITOR_LEN) #else #define XTENSA_SYS_TEXT_ADDR \ (MEMADDR(CFG_SYS_SDRAM_SIZE) - CONFIG_SYS_MONITOR_LEN)