Hi Simon,
On Thu, Jan 29, 2015 at 2:04 AM, Simon Glass sjg@chromium.org wrote:
Hi Bin,
On 28 January 2015 at 07:19, Bin Meng bmeng.cn@gmail.com wrote:
Quark SoC contains an embedded 512KiB SRAM (eSRAM) that is initialized by hardware. eSRAM is the ideal place to be used for Cache-As-RAM (CAR) before system memory is available.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/x86/cpu/quark/car.S | 105 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 105 insertions(+) create mode 100644 arch/x86/cpu/quark/car.S
diff --git a/arch/x86/cpu/quark/car.S b/arch/x86/cpu/quark/car.S new file mode 100644 index 0000000..6b7b249 --- /dev/null +++ b/arch/x86/cpu/quark/car.S @@ -0,0 +1,105 @@ +/*
- Copyright (C) 2015, Bin Meng bmeng.cn@gmail.com
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <config.h> +#include <asm/post.h> +#include <asm/arch/quark.h>
+.globl car_init +car_init:
post_code(POST_CAR_START)/** Quark SoC contains an embedded 512KiB SRAM (eSRAM) that is* initialized by hardware. eSRAM is the ideal place to be used* for Cache-As-RAM (CAR) before system memory is available.** Relocate this eSRAM to a suitable location in the physical* memory map and enable it.*//* Host Memory Bound Register P03h:R08h */mov $0x00030800, %eaxmov $(DRAM_BASE + DRAM_MAX_SIZE + ESRAM_SIZE), %edxlea 1f, %espjmp msg_port_write+1:
/* eSRAM Block Page Control Register P05h:R82h = 10000080h */mov $0x00058200, %eaxmov $0x10000080, %edxlea 2f, %espjmp msg_port_write+2:
post_code(POST_CAR_CPU_CACHE)jmp car_init_ret+msg_port_read:
/** Parameter:* EAX[23:16] - Message Port ID* EAX[15:08] - Register AddressCan we use lower case eax?
Yes.
** Return Value:* EAX - Message Port Register value** Return Address: ESP*//* opcode 0x10, all bytes enable 0xf0 */or $0x100000f0, %eax#define for this and other things in this file?
I will try.
mov %eax, %ebx/* Write MCR B0:D0:F0:RD0 */mov $0x800000d0, %eaxmov $0xcf8, %dxout %eax, %dxmov $0xcfc, %dxmov %ebx, %eaxout %eax, %dx/* Read MDR B0:D0:F0:RD4 */mov $0x800000d4, %eaxmov $0xcf8, %dxout %eax, %dxmov $0xcfc, %dxin %dx, %eaxjmp *%esp+msg_port_write:
/** Parameter:* EAX[23:16] - Message Port ID* EAX[15:08] - Register Address* EDX - Message Port Register value to write** Return Address: ESP*//* opcode 0x11, all bytes enable 0xf0 */or $0x110000f0, %eaxmov %eax, %esimov %edx, %edi/* Write MDR B0:D0:F0:RD4 */mov $0x800000d4, %eaxmov $0xcf8, %dxout %eax, %dxmov $0xcfc, %dxmov %edi, %eaxout %eax, %dx/* Write MCR B0:D0:F0:RD0 */mov $0x800000d0, %eaxmov $0xcf8, %dxout %eax, %dxmov $0xcfc, %dxmov %esi, %eaxout %eax, %dxjmp *%esp--
Regards, Bin